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Is that only load/store operations are not reordered around memory fences? My understanding is that serializing instructions such as CPUID prevent any instruction (including load/store operations) being reordered around it. Is it the same for memory fences?

chamibuddhika
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    Are you asking if `MFENCE` is a barrier for instructions that don't reference memory? No, it isn't, but you can't observe the reordering anyway other than `rdtsc`, and the insn reference manual documents what insns it's ordered with respect to. (On some specific microarchitectures, e.g. AMD Bulldozer-family, `MFENCE` is serializing for the whole pipeline, not just loads/stores, according to the AMD optimization manual. This is an implementation detail, not something that's architecturally guaranteed.) – Peter Cordes Apr 26 '16 at 00:06
  • Yes. MFENCE is what I meant. So am I right in understanding CPUID prevents any kind of instruction reordering? (Hence its usage coupled with rdtsc?) – chamibuddhika Apr 26 '16 at 01:09
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    Read the Intel insn reference manual (links in the x86 tag wiki). "CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution guarantees that any modifications to flags, registers, and memory for previous instructions are completed before the next instruction is fetched and executed." If you're using this for `rdtsc`, note that the `rdtscp` instruction has a one-way barrier effect built in. – Peter Cordes Apr 26 '16 at 01:34
  • Thanks. Just read it. That clears. – chamibuddhika Apr 26 '16 at 01:46
  • Possible duplicate of [Are loads and stores the only instructions that gets reordered?](https://stackoverflow.com/questions/50494658/are-loads-and-stores-the-only-instructions-that-gets-reordered) – Peter Cordes Jun 21 '18 at 04:33

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