make with argument for different executable name

Question

I have a c++ codebase. I have a CMakeLists. When I run make, it creates the binary myexec.

I would like to be able to run, say, make -- v2, and that it creates the exact same binary, but called myexec_v2. It would be great if it did not have to recompile everything to create this binary, but only the modified files.

How can I do that?

Not an answer, but couldn't a possible workaround be to write a small script that does 1) make and then 2) rename/copy `myexec` based on the argument using either 'move' or 'copy', whichever is suitable? — Kajal, May 19 '16 at 14:26
Does this help? http://stackoverflow.com/questions/6273608/how-to-pass-argument-to-makefile-from-command-line — corsel, May 20 '16 at 10:38

Lesmana · Answer 1 · 2020-04-13T16:50:06.180

myexec myexec_v2: $(prerequisites)
    @echo compile $@

observe:

$ make myexec
compile myexec
$ make myexec_v2
compile myexec_v2

if nothing else is needed to compile myexec_v2 then you are done.

see here for more information: https://www.gnu.org/software/make/manual/html_node/Multiple-Targets.html

here is a slightly more advanced version

myexec myexec_v2: myexec%: $(prerequisites)
    @echo compile $@ $*

this is called a static pattern rule. the myexec% in the middle is called the target pattern. in this example we only use it to get the so called stem. the stem would be _v2 and the variable $* expands to the stem.

for more information: https://www.gnu.org/software/make/manual/html_node/Static-Usage.html

observe:

$ make myexec
compile myexec
$ make myexec_v2
compile myexec_v2 _v2

now you can use either $@ or $* in the recipe to modify the behaviour to compile on or the other.

but if you want to do if branches in the recipe read this first: Basic if else statement in Makefile

make with argument for different executable name

1 Answers1