gcc -masm=intel gives me lowercase mnemonics

Question

Compiling a simple C program with with

gcc -masm=intel basic.c -o basic.asm

generated assembly like below :

.cfi_startproc
    push    rbp
    .cfi_def_cfa_offset 16
    .cfi_offset 6, -16
    mov rbp, rsp /I expected mov to be MOV
    .cfi_def_cfa_register 6
    mov QWORD PTR [rbp-8], OFFSET FLAT:.LC0
    mov eax, 0
    pop rbp /I expected pop to POP
    .cfi_def_cfa 7, 8
    ret
    .cfi_endproc

I am on an Intel X86_64 machine and in the Intel software developer's manual, I understand the mnemonics are represented all uppercase (which means they suggest using it?).

Is there an option with gcc that gives me uppercase mnemonics?

Answer 1

FYI, to strip out the "noise" in gcc asm output (.cfi directives, unused labels, etc.), see How to remove "noise" from GCC/clang assembly output?. TL:DR: just put your code on http://gcc.godbolt.org/

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In the Intel software developer's manual, the mnemonics are represented all uppercase (which means they suggest using it?).

I think they use all-uppercase as an alternative to code-formatting, so they can write stuff like "Performs a bitwise AND operation" without confusion (because "bitwise and operation" is also a valid English phrase). They could have gone with "perform a bitwise and operation", but they didn't.

Their use of all-caps for mnemonics and register names is not a suggestion that it's the right way to code. Intel's tutorials / articles often have chunks of asm code (like this one about detecting AVX). In Listing 1 of that, they use lowercase mnemonics and register names for everything except XGETBV, which I think they do to highlight it, because that's the new instruction that they're teaching you about. Their intrinsics guide also uses lower-case mnemonics in the field showing which instruction a mnemonic maps to (compiler optimization can choose different insns...).

Mnemonics and register names are not case-sensitive. Most people prefer lower-case. Good style also includes indenting your operands to a consistent column, and same for comments, so your code doesn't look all ragged. And always indent your code more than labels, so you can quickly see labels (branch targets). For example, this bit of the source for a golfed (smallest code-size) Adler-32 in x86-64 machine code illustrates what I think is reasonably good style.

; optimized for code-size, not speed
slow_small_addler32:
    xor     eax,eax         ; scratch reg for loading bytes
    cdq                     ; edx: high=0
    lea     edi, [rdx+1]    ; edi: low=1
    ;jrcxz  .end            ; We don't handle len=0.  unlike rep, loop only checks rcx after decrementing
.byteloop:
    lodsb                   ; upper 24b of eax stays zeroed (no partial-register stall on Intel P6/SnB-family CPUs, thanks to the xor-zeroing)
    add     edi, eax        ; low += zero_extend(buf[i])
    add     edx, edi        ; high += low
    loop   .byteloop      ; only use LOOP for small code-size, not speed
.end:
    ;; exit when ecx = 0, eax = last byte of buf
    ;; lodsb at this point would load the terminating 0 byte, conveniently leaving eax=0
 ... more code

See also this NASM style guide, linked from the x86 tag wiki.

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Is there an option with gcc that gives me uppercase mnemonics?

No. You could upcase instruction mnemonics and register names with sed or something if you wanted to. (But you'd have to be careful not to munge symbol names, which are case sensitive).

The pattern-matching in the scripts that power http://gcc.godbolt.org/ could maybe be useful for this, but I haven't looked much at the js source.