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Please explain $@ $^ $ in the makefile below

LIBS  = -lkernel32 -luser32 -lgdi32 -lopengl32
CFLAGS = -Wall

# (This should be the actual list of C files)
SRC=$(wildcard '*.c')

test: $(SRC)
    gcc -o $@ $^ $(CFLAGS) $(LIBS)
vehomzzz
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  • possible duplicate of [What do the makefile symbols $@ and $< mean?](http://stackoverflow.com/questions/3220277/what-do-the-makefile-symbols-and-mean) – Mark Leiber May 26 '15 at 13:58

2 Answers2

8

This is what these two symbols mean:

  • $@ is the target i.e. test
  • $^ is the list of pre-requisites for the rule (which in this case is the expanded wild card list as specified in SRC=$(wildcard '*.c'))

All such variables are explained in the Automatic variables page of the GNU make manual.

naught101
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t0mm13b
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  • What does 'expands the wildcard list as specified in `SRC=$(wildcard '*.c')`' mean? does it just result in `'*.c'`? – naught101 Apr 07 '14 at 06:21
  • Ah, it's a [file matching wildcard](https://www.gnu.org/software/make/manual/html_node/Wildcard-Function.html#Wildcard-Function). – naught101 Apr 07 '14 at 12:19
  • @naught101 It is stated explicitly in the answer *wild card list*, think of a shell glob for wildcards... :) – t0mm13b Apr 07 '14 at 12:21
  • Yeah. For a noob, it's pretty confusing, because a plain wildcard string works for depndencies (e.g. `*.c`, instead of `$(wildcard '*.c')`), but not in variables. – naught101 Apr 07 '14 at 12:25
2
SRC=$(wildcard '*.c')

This just all your source file name ending with .c ie file1.c, file2.c file3.c etc.

in 

test: $(SRC)
    gcc -o $@ $^ $(CFLAGS) $(LIBS)

$ is a way to define variables in Makefile

$@ is your target, in your case it is "test".

$^ is the list of all the prerequisites of the rule, including the names of the directories in which they were found

$< is the list of all dependencies

ref: https://www.gnu.org/software/make/manual/make.html#Automatic-Variables

Rahul
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