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The makefile has multiple targets which will called for all files in the directory. The automatic variable does not get replaced for the target.

TARGETS += txyz_abc txyz_def
.PHONY: all clean
all: $(TARGETS)

txyz_abc: $(UY_DIR)/$(OBJ)/support.o \
    $(UX_DIR)/$(OBJ)/%.o
    $(CC) $(CFLAGS) -c $< -o $@

$(UX_DIR)/$(OBJ)/%.o: %.c
    $(call mkdir, $(UX_DIR)/$(OBJ))
    $(CC) $(CFLAGS) -c $< -o $@

$(UY_DIR)/$(OBJ)/support.o: $(UY_DIR)/src/support.c
     $(call mkdir, $(UY_DIR)/$(OBJ))
     $(CC) $(CFLAGS) -c -o $@ $<

on make support.o is generated. but throws an error that no rule to make target '../ux_src/obj/%.o", needed by 'txyz_abc'.

adams.p
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  • Why are you using the \ character here: txyz_abc: $(UY_DIR)/$(OBJ)/support.o \ ? Joining lines and at the same time trying to run them doesn't make sense. – 2501 Sep 30 '16 at 08:08
  • 1.txyz_abc will have multiple target like $(UY_DIR)/$(OBJ)/%.o. 2. $(UY_DIR)/$(OBJ)/%.o will be called from txyz_def also. So it will take the target names automatically. – adams.p Sep 30 '16 at 08:40
  • @adams.p `%` in a `make` rule is something like a placeholder for the loop variable in a "for each" loop. In order for there to be a `%` in the dependency and command part it has to be created by being "declared" in the target (left of the `:`). Your target `txyz_abc` has no `%`, so there is no placeholder `%` in that make rule. – Klas Lindbäck Sep 30 '16 at 10:23
  • I think this answer could help you (it is a bit overkill, but I'm sure you can strip it down to what you need): http://stackoverflow.com/a/5657135/646887 – Klas Lindbäck Sep 30 '16 at 10:25
  • Or this answer, which lists two ways to do what you need: http://stackoverflow.com/a/14289872/646887 – Klas Lindbäck Sep 30 '16 at 10:27
  • @adams.p If answers Klas posted answer your question, let me know, so i can mark this as a duplicate. Alternatively you can answer the question if you found the solution. – 2501 Sep 30 '16 at 12:53

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