10

I am using a library which has a sample application. The sample makefile contains $< in the arguments:

all:test.cpp
    g++ -Wl,--no-as-needed -o Example $<
clean:
    rm -f SampleApp11

I've looked this up and tutorialspoint say that

$< the name of the related file that caused the action.

Another website states that:

this is a suffix replacement rule for building .o's from .c's it uses automatic variables $<: the name of the prerequisite of the rule(a .c file) and $@: the name of the target of the rule (a .o file) (see the gnu make manual section about automatic variables) .c.o: $(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@

I am still confused, what does this means?

Jonas Schäfer
  • 20,140
  • 5
  • 55
  • 69
  • In your example its the **first** dependency (file) after the `all:` target - `test.cpp`. – Galik Oct 08 '16 at 10:51
  • Ahh, so `<$` tells g++ which file to compile, is that correct? –  Oct 08 '16 at 10:53
  • 12
    Note that this has nothing to do with g++. It's make which replaces this before calling g++. g++ never sees `$<`. If it did, it would treat it as a file name, and likely issue an error message about no file by that name being found. –  Oct 08 '16 at 10:56
  • Changing the line to `echo test: $<` would have told you what it does, then you could have looked it up in the documentation for the right tool (_not_ GCC!) to learn what it means. Try to get used to performing research and experimentation in this manner. – Lightness Races in Orbit Oct 08 '16 at 13:37
  • @LightnessRacesinOrbit Apologies, I did a significant amount of research and was still unclear/confused. It's my first week of writing C/C++ code and compiling it - my previous experience was with interpreted languages. –  Oct 08 '16 at 14:23
  • I'm sure that even in the world of interpreted languages you are familiar with performing research and experimentation :) – Lightness Races in Orbit Oct 08 '16 at 14:42

2 Answers2

17

This is actually nothing to do with the compiler, its part of the Makefile syntax and it is substituted before the compiler is run.

In your example it's the first dependency (file) after the all: target - test.cpp.

The basic function of the Makefile is to create a target if a dependency changes:

target: dependency.cpp
    rule to create target (using dependency.cpp)

Typically $< is the input to the compiler and $@ is the output.

It's sort of as if it was this (not a valid Makefile):

$@: $<
    g++ -o $@ $<

The way I remember them is @ resembles a target (as in target practice) and < resembles an arrow. So I imagine an arrow pointing to a target:

@ <-------- (think "Robin Hood")

YMMV

Galik
  • 47,303
  • 4
  • 80
  • 117
9

It is one of GNU make's automatic variables.

The name of the first prerequisite. If the target got its recipe from an implicit rule, this will be the first prerequisite added by the implicit rule (see Implicit Rules).

A prerequisite is a file listed in the rule:

targets : prerequisites
        recipe

For example, in the following rule the first prerequisite is test.c file:

my_executable: test.c precompiled.o
    g++ -o my_executable $<

It is equivalent to the following:

my_executable: test.c precompiled.o
    g++ -o my_executable test.c

And the precompiled.o is the second prerequisite (a precompiled object file implied).

Lightness Races in Orbit
  • 378,754
  • 76
  • 643
  • 1,055
Ruslan Osmanov
  • 20,486
  • 7
  • 46
  • 60