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I am confused with the clock system on my STM32F7 device (Cortex-M7 microcontroller from STMicroelectronics). The reference manual does not clarify the differences between these clocks sufficiently:

  • SYSCLK
  • HCLK
  • FCLK

The reference manual reads in chapter << 5.2 Clocks >> "The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock (HCLK) divided by 8."
This statement contradicts the figure from CubeMX. Notice that in CubeMX I can choose myself the prescaler from HCLK to 'Cortex System Timer'. It is not necessarily a division by 8.

enter image description here

K.Mulier
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  • Note that SYSCLK != SysTick. SYSCLK is the "system clock", generated by the System Clock Generation Unit (SCGU), used to drive the CPU and buses. SysTick is the ARMv7-M standard "system tick" timer commonly used as timebase in real-time operating systems. – claymation Feb 15 '21 at 02:21
  • Interesting @claymation, thanks for this comment :-) – K.Mulier Feb 16 '21 at 11:55
  • Also look at `Core and bus clock generation` diagram on device reference manual, thats insightfull. – mohammadsdtmnd Apr 27 '22 at 12:06

1 Answers1

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Normally the only difference between HCLK and FCLK is that :

  • HCLK is the main CPU clock, also used for AHB interface. It can be gated when the CPU is sleeping (WFI for example)
  • FCLK is synchronous to HCLK but is not gated when the CPU goes to sleep, so that it can awake in case of interrupt.
Dric512
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  • Thank you sir. What do you mean by "gated"? Is the SYSCLK just an intermediate clock signal from which HCLK and FCLK are derived, but not actually used itself? – K.Mulier Oct 24 '16 at 11:51
  • Yes this is what I understand from the diagram; By gated, I mean that the clock can be stopped to save power when not needed. – Dric512 Oct 24 '16 at 19:50
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    Gated means it goes through a gate. In particular an AND gate, look at all of the clock enable bits in the RCC registers, those individual bits for those individual peripherals/logic blocks are essentially ANDed with a clock, (sometimes the inverse is anded). Stopping clock edges on blocks of logic saves a lot of power and is very common in "microcontrollers". Very hard to call a cortex-m7 a microcontroller, but it does fall into that class. – old_timer Oct 25 '16 at 03:37
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    Note holding something in reset and still enabling the clock doesnt necessarily mean low or lowest power so the clock gates are there to prevent that clock from cascading through that block possibly flipping implementations of combinational gates (and consuming power). – old_timer Oct 25 '16 at 03:38
  • Thank you @dwelch , this really clarifies a lot :-) – K.Mulier Oct 25 '16 at 08:45
  • So now I know that HCLK is gated, and FCLK is not. But what is the actual different use of them? Will FCLK drive the Cortex core and HCLK the peripherals? – K.Mulier Oct 25 '16 at 08:47
  • This is actually tied and you do not have control about it. They have the same frequency divider so have the same frequency. Some parts of the CPU use on clock or the other but you cannot change it. In the same way, the clock gating control is inside the CPU so you cannot change it or control it (Except executing instructions that cause the CPU to go to sleep). – Dric512 Oct 25 '16 at 18:06
  • so can we use SYSCLK for i2c ? – Robokishan Aug 16 '20 at 18:58
  • Of course you can use SYSCLK for i²c, the gate to control its clock is shown right in the middle of the diagram and one of its inputs is, surprise, SYSCLK. – Matthias Urlichs Oct 10 '21 at 15:57