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I am undefeated in a question like this

In the context of a memory hierarchy why implement data cache and instruction cache?

I replied that it is useful to decrease the number of conflict miss and insufficient space miss. But the data cache and the instruction cache can be sized according to the number of data and instruction? Because i assumed that the number of data is higher than the number of instruction (many times we need 2 data to execute 1 instruction) and the data cache and instruction cache is sized according to this numbers. Is true or completely wrong? In the case that it's wrong, why implement data cache and instruction cache to reduce miss?

Peter Cordes
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nene4496
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  • It's impossible to understand what the question means from the way it's worded. Why have a cache of each type? why should they be split? You should go back to whoever asked it for clarifications. – Leeor Nov 21 '16 at 21:11
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    See [my answer on another cache question](http://stackoverflow.com/questions/4666728/why-is-the-size-of-l1-cache-smaller-than-that-of-the-l2-cache-in-most-of-the-pro/38549736#38549736) where I point out that one large cache with enough read/write ports for instructions and data would be more power hungry, and/or impossible to make as fast as split L1 caches. Data and instructions usually don't overlap, so split caches are almost pure win. – Peter Cordes Nov 21 '16 at 21:26
  • @Ernest Fish Moro Please read the excellent answer provided by Peter Cordes in his comment. – Reinhard Männer Nov 22 '16 at 08:25

2 Answers2

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The idea of a cache is to deliver cached data in 1 cycle to keep the CPU running at maximum speed.

Now today all CPUs are pipelined. This means the they have independent modules that e.g. fetch an instruction, decode it, fetch the operands, execute the instruction, and write back the result. All of these pipeline stages are executed whenever possible at the same time for different instructions.
For maximum speed, an instruction fetch has to be done at the same time as an operand fetch of an earlier instruction decoded before. Both can only be done (in the optimal case) at the same time in 1 cycle if one has an instruction cache and a data cache.

Reinhard Männer
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  • You can build a cache with two read ports. In fact, modern x86 designs do so for their L1D caches (Intel since SnB, AMD since K8). Haswell even can even do two 32B loads and one 32B store per clock, and probably also transfer data to/from L2 at the same time, so that's a lot of ports. So it's not impossible to read instructions and data in parallel from the same cache, it's just a waste of transistors / power, like I commented on the question. Still, upvoted as close enough to correct for an oversimplified explanation. – Peter Cordes Nov 21 '16 at 22:01
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    @ Peter Cordes I just read your excellent answer to this other question, which you mentioned in your comment above. Thanks a lot for this detailed clarification! – Reinhard Männer Nov 22 '16 at 08:23
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Another possible reason to have two caches (Instruction and Data) is Thrashing. Imagine a situation where your instruction and data reside in two memory locations whose index bits are the same. Assuming a direct mapped cache, (cheeky I know), It goes like this.

  1. Fetch instruction from memory, calculate the index and store store it there.
  2. Decode the instruction and get the address of data.
  3. Now fetch the data from memory, calculate the index to store data.
  4. There is some data in that location, well too bad, flush it to next level cache and store the newly fetched data.
  5. Execute the instruction.
  6. Its time to decode the next instruction, well its a cache miss as we swapped the cache entry for our data. Now go fetch it again.
  7. When we fetch it we have to replace our data again as it has the same index.

So we will be continually swapping data and instruction form the same cache line, aka thrashing.

Isuru H
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