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How would you achieve 128-bit atomic operations in x86?

Intel's System Programming Guide, Part 1, 8.1 Locked Atomic Operations specifies guaranteed 16-, 32-, and 64-bit atomic operations. So, can you achieve 128-bit atomic operations by doing 2 64-bit ops with the LOCK prefix? Something like...

LOCK mov 64bits->addr
LOCK mov 64bits->addr+64bits

Aparently SSE has 128-bit XMM registers. Can you just do 128-bit compare-and-swap using these registers?

brooksbp
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1 Answers1

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The LOCK Prefix can not be used in combination with MOV instruction.

The LOCK prefix can be prepended only to the following instructions and only to those forms of the instructions where the destination operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. Intel Instruction Set Reference

Doing so will generate an Invalid Opcode Exception. So LOCK CMPXCHG16B is the only way here.

bkausbk
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  • Concerning Intel Instruction Set Reference a 'LOCK' is required. "This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the interface to the processor’s bus, the destination operand receives a write cycle without regard to the result of the comparison." – bkausbk Jul 14 '11 at 07:28
  • @brooksbp: there are [use-cases for `cmpxchg` without `lock`](https://stackoverflow.com/a/44273130/224132), e.g. uniprocessor systems for use on memory other than an MMIO port. That also makes it consistent with memory-destination `add` and other instructions that do have obvious uses other than concurrency. – Peter Cordes Nov 27 '17 at 09:52