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In general hardware interrupts need to be processed immediately, at least so as to acknowledge it and do some first level of processing. As I understand this is not scheduled activity. Please correct me.

So the question is how to choose a processor that would actually execute this hardware interrupt handler?

One can answer this for Linux and/or BSD systems

ultimate cause
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  • AFAIK mainline Linux only supports SMP, symmetric multi-processor hardware, meaning any processor can service interrupts. I have seen UNIX ported to asymmetric hardware, i.e. there's a processor dedicated to I/O and interrupts. BTW a processor does not *"execute interrupt"*. It can *service* an interrupt, i.e. execute an interrupt service routine, ISR. – sawdust Dec 27 '16 at 07:28
  • Wait, UP is supported as well. – 0andriy Dec 28 '16 at 23:08

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In general, this depends on the functionality offered by multi-core processor and OS. While using multi-core processors, you might need to configure the affinity of the interrupt as per your requirement.

In the case of linux, the /proc file system has provision to show/configure the affinity of interrupts.

1) The file smp_affinity for respective irq holds a bitmask which can be used for configuring the irq to be serviced by respective core in multi-core system :

/proc/irq/'irq_number'/smp_affinity

echo 2 > /proc/irq/12/smp_affinity  -> Configures the affinity of IRQ 12 to CPU 1
echo 4 > /proc/irq/14/smp_affinity  -> Configures the affinity of IRQ 14 to CPU 2

2) The file smp_affinity_list helps in configuring a range of CPU for a particular IRQ by avoiding the method of bitmask to configure the cores :

/proc/irq/'irq_number'/smp_affinity_list

cat /proc/irq/12/smp_affinity_list -> Configures the affinity of IRQ 12 to CPU cores 0 to 3

3) Also linux offers a interrupts load balancing daemon called irqbalance which can help in distribution of interrupts across processor cores to optimize performance. This daemon may be enabled by default in certain system and hence this should be disabled if you want the manually configure the affinity of interrupt else this might override the configured affinity after every reset.

Karthik Balaguru
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Choosing a particular processor for handling an interrupt is determined with the help of configuring registers on IO-APIC(on the IO controller hub) and Local APIC(on the processor).

IO-APIC and Local APIC communicate over an APIC bus where it will be decided which processor would handle the broadcasted interrupt among other things. On IO-APIC, there is something called a Redirection Table which can be programmed to indicate the destination processor, interrupt vector etc. for a particular IRQ line.

In the words of Ingo Molnar: "Most (all) Intel-MP compliant SMP boards have the so-called ‘IO-APIC’, which is an enhanced interrupt controller. It enables us to route hardware interrupts to multiple CPUs, or to CPU groups. Without an IO-APIC, interrupts from hardware will be delivered only to the CPU which boots the operating system (usually CPU#0)."

Source: https://www.kernel.org/doc/html/latest/x86/i386/IO-APIC.html

For the information of various registers(this page contains link for IO-APIC specifications as well): https://wiki.osdev.org/APIC

Modern motherboards make use of MSIs(Message Signaled Interrupts) to deliver interrupts. MSIs don't require IO-APIC but Local APIC on the processor is still needed. Here the same thing is achieved with the help of "Root Complex", "Switch" and "PCI/PIC-X to PCIe Bridge" but the basic concept remains same.

Shariq Ehsan
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It truly depends upon the operating system implementation.

Some assign a all interrupts to a single processor, while others distribute the interrupt handling across some or all of the processors.

On NUMA systems, the operating system should attempt to assign interrupt handling to a "nearby" processor.

You'll have to read the source of the operating system (and version) you're interested in to figure out what it uses.

Eric Schnoebelen
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  • Thanks for your answer +1. Wanted to be sure that your answer is about hardware interrupts, and not the bottom half processing which is actually a scheduled activity. – ultimate cause Dec 26 '16 at 07:25
  • I wasn't differentiating between the "bottom half" of the interrupt handler and the hardware interrupt. But some hardware systems may wire hardware interrupts to a subset of processors, or even a single processor, making the operating system even more interesting. (remember, there is more to the world than X86 in the IBM-PC/AT system architecture.) – Eric Schnoebelen Dec 26 '16 at 17:55
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    It partially depends on OS implementation, More strongly it depends on hardware implementations of PICs, PIRs, etc. – 0andriy Dec 26 '16 at 21:40
  • @EricSchnoebelen - What portion of it should depend upon OS implementation? I could not think of anything other than hardwired digital circuit. Because in hardware interrupts it would only be digital pulses playing their role right from device to interrupt controller to processor. Only after the pulse reaches to processor OS may start its job. How come it plays role before that? – ultimate cause Dec 27 '16 at 05:23