Makefile error in C linux

Question

I have an error while making my makefile in linux. Here's my code:

CC = gcc
CFLAGS = -Wall -m32 -g -fno-stack-protector -z execstack -O0
SHELL_SOURCES = Shell.c

SHELL = Shell

.PHONY: all target1 clean

all: target1 

target1: $(SHELL)

$(SHELL): $(SHELL_SOURCES)
    $(CC) $(CFLAGS) $^ -o $@

clean:
rm -rf $(SHELL)

The error I get is:

gcc -Wall -m32 -g -fno-stack-protector -z execstack -O0 Shell.c -o Shell
make: Shell: Command not found
Makefile:16: recipe for target 'Shell' failed
make: *** [Shell] Error 127

Answer 1

You can't use SHELL as a variable in a Makefile, it is used to know what shell (/bin/sh, /bin/bash, etc) will be used in your Makefile.

CC = gcc
CFLAGS = -Wall -m32 -g -fno-stack-protector -z execstack -O0
EXE_SOURCES = Shell.c

EXE = Shell


.PHONY: all target1 clean

all: target1 

target1: $(EXE)

$(EXE): $(EXE_SOURCES)
    $(CC) $(CFLAGS) $^ -o $@

clean:
    rm -rf $(EXE)

Answer 2

Take more time to read documentation of GNU make

You should remove spaces around variable assignments, e.g. code

 CC= gcc

Beware that tab characters are significant in Makefile-s (in rules, for their action lines). Use some editor aware of that (e.g. emacs has a mode for Makefile). See also this example (but the rule action should really start with a tab character). Notably, you need a tab just before the $(CC) $(CFLAGS) $^ -o $@ and another one before rm.

Consider also using remake -x to debug your Makefile, or at least make --trace

But the main bug was indeed, as answered by Cpatricio, to use the SHELL variable. Be careful when using variables or names already known to make. Actually, I have the habit of prefixing my make variable names with a common prefix, so you could have defined your variables like JOJOIGA_SOURCES=$(wildcard *.c), JOJOIGA_SHELL=Shell etc....