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I'm trying to write a Makefile rule that checks multiple environment variables to ensure that they are defined. This is close to Makefile variable as prerequisite but I'm trying to loop over multiple variables. In other words, I'm trying to write this more concisely:

check-env:
ifndef ENV1
    $(error ENV1 is undefined)
endif
ifndef ENV2
    $(error ENV2 is undefined)
endif
ifndef ENV3
    $(error ENV3 is undefined)
endif

I've tried to use foreach without success, since it looks like ifndef is evaluated before the foreach.

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Quentin Pradet
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1 Answers1

4

Makefile:

variables := a b c

fatal_if_undefined = $(if $(findstring undefined,$(origin $1)),$(error Error: variable [$1] is undefined))
$(foreach 1,$(variables),$(fatal_if_undefined))

all:

Running:

$ make -f Makefile.sample
Makefile.sample:4: *** Error: variable [a] is undefined.  Stop.

$ make -f Makefile.sample a=10 b=2
Makefile.sample:4: *** Error: variable [c] is undefined.  Stop.

$ make -f Makefile.sample a=10 b=2 c=5
make: Nothing to be done for 'all'.
Alexey Semenyuk
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