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Using "C", how do I programatically change cache sizes on an Ubuntu Linux 16.04 Dell, Lenovo or Hewlett Packard 64 bit machine?

Here are two URLS of software engineering atricles that touch upon this subject.

https://unix.stackexchange.com/questions/253816/restrict-size-of-buffer-cache-in-linux

How does one write code that best utilizes the CPU cache to improve performance?

Yet, do not tackle the question of either disabling or enabling L2 cache in a multilevel caching hierarchy or decreasing L2 cache size.

Any help is greatly appreciated.

Community
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Francis Tuan
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  • The first link has nothing to do with CPU cache and is irrelevant if you're talking about L2 cache. Can you explain the use cases where you think this might be helpful, because this smells like a XY problem - http://meta.stackexchange.com/questions/66377/what-is-the-xy-problem – Joe Feb 26 '17 at 23:00
  • The first article talks about virtual memory, which is a very different thing. As far as I know, the L2 cache is baked into the CPU. It seems like you'd need a pretty exotic use-case to benefit from disabling it or decreasing its size. – Richard Feb 26 '17 at 23:02
  • @Joe, Thank you for your excellent comment. I wish to change L2 cache size when running an lengthy time(12+ hours) experiment to transform a large random complete hypercube graph with 131,072 vertices into a minimum spanning tree using Prim's algortithm which I would like to speed up using CPU caching cleverly and correctly. Thank you. – Francis Tuan Feb 26 '17 at 23:07
  • @Richard, I really respect your pertinent comment about the exotic use-case. Here it is: . I wish to change L2 cache size when running an lengthy time(12+ hours) experiment to transform a large random complete hypercube graph with 131,072 vertices into a minimum spanning tree using Prim's algortithm which I would like to speed up using CPU caching cleverly and correctly. How might I programmatically disable it or decrease it's size? What about mmap()(i.e. Memory mapping)? Thanks. – Francis Tuan Feb 26 '17 at 23:11

2 Answers2

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You cannot enable, disable, shrink or expand the L2, L1, or indeed any other cache. They're there, they do their thing, and that's it. I know of no CPU in history (corrections welcome) where cache has been a flexibly programmable thing.

You almost never, ever have to worry about the cache and what it does, and it's only in extremis where one is scraping up the very last drop of performance does one need to worry about the cache, and even then it's much more efficient to get hold of an optmised math library than to endeavour to write one of one's own.

Some CPUs have the option for software to drop hints as to what data would be good to load. One example is the PowerPCs, and such instructions were very useful in getting the most out of the CPU core itself when doing things like FFTs, etc.

The only high performance CPU in recent history that has been cache-less is the Cell processor as found inside the PlayStation 3; the 8 SPEs had no cache, but did have 256kbyte of SRAM instead which was actually quite useful.

bazza
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  • Thank you for your excellent answer. How might I drop hints as to what segment of data such as an adjanceny list or adjancency matrix would be good to load. I am upvoting your answer right now. May I ask if mmap() or munmap() is connected to the context of this question? Thank you. – Francis Tuan Feb 26 '17 at 23:37
  • @FrancisTuan http://stackoverflow.com/questions/36563277/x86-64-cache-load-and-eviction-instruction. Though you have to try really hard to beat the built in pre-fetchers. Intel's whole design philosphy is based on making all software perform pretty well, and they're very good at it. You have to try very hard to beat the built in prefetch, especially if there's other tasks running too. The Cell processor took the opposite point of view - it left "prefetch" entirely up to the programmer which was truly great for high performance maths (video streaming, DSP, etc). – bazza Feb 27 '17 at 08:09
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Matthew Caesar from the Department of Computer Science University of California, Davis authored a nice article titled "Performance and Analysis of Minimum Spanning Tree Algorithms in Cache Based Architectures" in which he used C++ software optimizations such as changing the Heap Fanout variation in Prim’s algorithm to use a d-ary heap so as to prefetch larger groups of random graph siblings so as to speed up the runtime significantly, https://pdfs.semanticscholar.org/bd1f/b82d4f4f4fa1041e9336c7d5c74023ebacb0.pdf.

Frank
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