Under frequency causing data corruption on ARM CortexM0+ based SoC?

Question

I'm working on a SoC test board, based on ARM Cortex M0+. The SoC is equipped with 5 memory banks and is capable of voltage and frequency scaling. But the issue i'm facing is, when ever I write some data/value to r/w registers at some address with some frequency lower than default frequency (20.8 MHz), is causing data corruption in such a way that each value is being written at multiple register addresses, despite of one value at one address. Code looks as follows:

int main(void) 
{
    //AP_PLL->CLKREF_RM = 0x000104f6; //32768 * 0x4F6 => 41.7 MHz; 
    //AP_PLL->CLKREF_RM = 0x0001027b; //32768 * 0x27b => 20.8 MHz;
    AP_PLL->CLKREF_RM = 0x00010140; //32768 * 0x4F6 = 10.8 MHz; 

    for (int i = 0; i < 200; i++)
    {
        *((unsigned int*) 0x1000 + i) = i;
    }

    return 0;
}

output when running at 10 Mhz : 0L, 0L, 1L, 1L, 1L, 1L, 2L, 2L, 3L, 3L, 4L, 4L, 4L, 4L, 4L, 5L, 5L, 6L, 6L, 6L, 6L

expected output : 0L, 1L, 2L, 3L, 4L, 5L, 6L, 7L, 8L, 9L, 10L

Are these memory banks accessed via some time-sensative interface? — Alexander, Mar 01 '17 at 18:01
what chip is this the arm part is probably irrelevant it is something in the chip. is this a SAMD21? — old_timer, Mar 01 '17 at 18:13
20.8 sounds both strange and too fast for being a default frequency 4,8,16 are more typical. — old_timer, Mar 01 '17 at 18:13
and dont know of a pll you can just jam something in and change frequency, generally there is a procedure with polling points to wait for things to settle. — old_timer, Mar 01 '17 at 18:14
@old_timer, 1. No, it is not SAMD21, but the SoC design is similar to that. 2. The hardware that I'm working, can be configured with in a discrete range of clock frequencies. Based on some parameters, I can easily adjust the processor to desired frequency (Other possible frequencies are approximately 10.4, 5.2, 3.3 etc.) 3. I even gave a long delay (1 sec) to check the settling time, but no use. 4. It is SRAM by the way not the regs on ARM. — SSR, Mar 01 '17 at 19:34
@FreddieChopin I'm using USB-to-SPI based (cp2130) bridge controller to debug and read the values at that registers. It is a 32bit register, by the way. Thanks — SSR, Mar 01 '17 at 19:36
the atmel design in the samd21 had rules for crossing clock domains and polling required for crossing those domains. are you in that situation again assuming it is not a pll setup issue? — old_timer, Mar 01 '17 at 19:49

Clifford · Answer 1 · 2017-03-01T21:22:06.907

3

Cortex-M0+ does not define a PLL - that is part specific, so since you have not divulged the specific part it is hard to advise specifically.

Normally, following a PLL frequency change it is necessary to wait for the PLL-lock to be achieved before switching to the PLL clock and continuing execution - in your example the memory access occurs while the PLL is in use and unstable and no doubt still to achieve lock.

Depending on the specific part and the nature of the clock source, PLL lock may take several tens of microseconds. Normally the PLL will have a status register that should be polled for lock status before switching to the PLL clock.

The normal clock switching process is:

Switch to a primary fixed frequency oscillator
Set the PLL configuration
Wait for PLL lock
Switch to the PLL oscillator

edited Mar 01 '17 at 21:22

answered Mar 01 '17 at 20:45

Clifford

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Hi @Clifford, Thanks for your answer. Can you suggest or share information about any hardware platform, that follows these steps in switching the PLL-frequency? – SSR Mar 29 '17 at 11:54
@SSR : I am not sure what you are asking for; the clock switch sequence is to be implemented in software, not hardware. Given that you already have hardware, I am not sure how other examples would help. It would be far simpler if you just clarified exactly what SoC you are using, so there would be no need to be quite so general. – Clifford Mar 29 '17 at 14:54

Under frequency causing data corruption on ARM CortexM0+ based SoC?

1 Answers1