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In the Intel x86 Instruction Set Reference, there are a number of AVX-512 instructions that have an optional {er} in the instruction. For example, one form of VADDPD is defined as 

EVEX.NDS.512.66.0F.W1 58 /r
VADDPD zmm1 {k1}{z}, zmm2,
zmm3/m512/m64bcst{er}

What does the {er} mean?

Mysticial
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GregoryComer
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    {er} means the MXCSR rounding mode can be overridden for the instruction – Michael Petch Apr 27 '17 at 04:14
  • What is the syntax for doing this? – GregoryComer Apr 27 '17 at 04:17
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    An example `VADDPD zmm0 {k1},zmm1,zmm3,{rz-sae}` . You can find information and some examples in the [architecture instruction set extensions programming reference](https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf) – Michael Petch Apr 27 '17 at 05:07

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From Intel SDM Volume 2A, 3.1.1.3 " Instruction Column in the Opcode Summary Table":

{er} — Indicates support for embedded rounding control, which is only applicable to the register-register form of the instruction. This also implies support for SAE (Suppress All Exceptions).

Section 2.6.8 a bit earlier states that {er}, when applicable, can be encoded in EVEX.L´L:

Static rounding control embedded in the EVEX encoding system applies only to register-to-register flavor of floating-point instructions with rounding semantic at two distinct vector lengths: (i) scalar, (ii) 512-bit. In both cases, the field EVEX.L’L expresses rounding mode control overriding MXCSR.RC if EVEX.b is set. When EVEX.b is set, “suppress all exceptions” is implied. The processor behaves as if all MXCSR masking controls are set.

Grigory Rechistov
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