What would be the minimal Makefile for a C project?

Question

I find plenty of answers such as this one that doesn't use the implicit rules.

The minimum I can write is this:

SRC = $(wildcard *.c)
OBJ = $(patsubst %.c, %.o, $(SRC))

EXEC=a.exe

all: $(EXEC)

$(EXEC): $(OBJ)
    $(CC) $^ -o $@

clean:
    $(RM) $(OBJ)
    $(RM) $(EXEC)

But I am sure I can remove the linking part as well.

Is it possible to reduce this Makefile a bit more?

EDIT

With the help of Maxim Egorushkin I wrote this:

#Makefile
OBJS=$(patsubst %.c,%.o,$(wildcard *.c))

EXEC=a

$(EXEC): $(OBJS)

all : $(EXEC)

clean :
    rm -f $(OBJS)

.PHONY: all clean

It does build my files, but it doesn't link anything:

$ make
cc    -c -o bar.o bar.c
cc    -c -o cow.o cow.c
cc    -c -o foo.o foo.c

What should I change?

The dummy source files are created as follow:

echo "int main() {return 0;}" > cow.c
touch foo.c bar.c cow.c

A minimal makefile is empty, using only predefined rules. – Thomas Dickey Jun 26 '17 at 09:23 — Thomas Dickey, Jun 26 '17 at 09:23

Maxim Egorushkin · Accepted Answer · 2017-08-17T12:23:55.830

3

The bare minimum would be:

all : a

a : a.o b.o c.o

clean :
    rm -f a a.o

.PHONY: all clean

It expects source files a.c, b.c and c.c to produce executable a:

$ touch a.c b.c c.c

$ make
cc    -c -o a.o a.c
cc    -c -o b.o b.c
cc    -c -o c.o c.c
cc   a.o b.o c.o   -o a
/usr/lib/gcc/x86_64-redhat-linux/5.3.1/../../../../lib64/crt1.o: In function `_start':
(.text+0x20): undefined reference to `main'
collect2: error: ld returned 1 exit status
<builtin>: recipe for target 'a' failed
make: *** [a] Error 1

However, you do not get automatic header dependency generation with the built-in GNU make rules. Extra 5 lines would be required for that.

edited Aug 17 '17 at 12:23

answered Jun 26 '17 at 09:56

Maxim Egorushkin

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You remove `a.c` in your clean target and you don't use the `$(RM)` variable – nowox Jun 27 '17 at 08:25
In my example I get `No rule to make target 'a', needed by 'all'` – nowox Jun 27 '17 at 08:26
@nowox I tested the code and it works. How do you invoke `make`? – Maxim Egorushkin Jun 27 '17 at 08:57
It works because you don't need to link your objects. In my example I have several C files. – nowox Jun 27 '17 at 08:59
@nowox In this case just add a dependency: `a: a.o several.o c.o files.o`. It is explained in the first link in my post. – Maxim Egorushkin Jun 27 '17 at 09:05
Any news from my last comment. I would like to give you reward, but I need your answer to be correct. – nowox Aug 16 '17 at 08:20
@nowox Did you overlook my previous comment? – Maxim Egorushkin Aug 17 '17 at 11:04
Yes I did. I have just edited my question so you can show me how your solution works – nowox Aug 17 '17 at 11:13
To use the built-in rule for linking `a.exe` there must be an object file named `a.exe.o`, which in turn requires source file `a.exe.c`. Otherwise you need to use your own linking rule. – Maxim Egorushkin Aug 17 '17 at 11:17
@nowox My answer is a working example. It requires a file named `a.c`. – Maxim Egorushkin Aug 17 '17 at 11:19
@nowox Updated with more instructions for you. – Maxim Egorushkin Aug 17 '17 at 12:24

What would be the minimal Makefile for a C project?

1 Answers1