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Intel Skylake has a single, "unified" scheduler (drawing on the left from WikiChip).

AMD Zen uses separate schedulers for each integer execution unit and one scheduler for the floating point execution units (drawing on the right from WikiChip, which took it from an AMD presentation).

What are the advantages and disadvantages of either design?

How does it affect micro-optimization of x86 code? (I know that this can get quite complex and subtle, see e.g. How are x86 uops scheduled, exactly? for a related question that, at the time of writing, was more specific to Intel CPUs with its unified scheduler).

Manuel Jacob
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    I think one advantage of a unified scheduler is that the entire size is available for finding ILP in code that's almost all SIMD ALU, for example. In an AMD CPU, if most of your uops only go to one domain, your OOO window-size is limited by that scheduler. IDK much about how AMD CPUs schedule, though, so I'm not sure what advantages that has (other than maybe power or being easier in some ways to design) . – Peter Cordes Aug 17 '17 at 06:41
  • IDK if AMD schedules uops to ports at issue/rename time like Intel does, or if the separate scheduler domains let uops sit in the scheduler and be checked against any port they can run on every cycle. – Peter Cordes Aug 17 '17 at 06:43

1 Answers1

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The advantages of the split scheduler could be

  1. They are smaller so use a couple of circuits less and the internal distance is shorter.
  2. They can be placed closer to their function units.
  3. The individual decisions are smaller as they can only go to fewer internal units.

The disadvantages could be:

  1. There is less instructions to schedule from, which becomes a problem when there are many more instructions of one type than of the other.
  2. If a unit is filled with instructions that could potentially be run on another there is extra wiring to reschedule on the other unit.
Surt
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