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I'm attempting to build a loadable kernel module dependent on several source files, but I'm getting this error:

/home/.../Uart.h:3:28: fatal error: linux/spinlock.h: No such file or directory
 #include <linux/spinlock.h>
                            ^

The main module code is all in one file (call it "xdev.c"). The dependencies are mostly functions that I need to call in the module and are included by their header files. I have the files organized like this:

./
    bin/
        This is where I want the compiled dependencies (.o files to go)
    src/
        My dependencies .c and .h files
        ...
        Uart.h  # Error is in this file
        Uart.c
        Crc8.h
        Crc8.c
        ...
    xdev.c      # This file include <linux/...> files with no trouble
    Makefile

I'm new to using make files, but based on tutorials and questions here, primarily this one, I created this make file:

TARGET = xdev

LINKER = gcc

# None of the compiler or linker flags I have tried worked, so I removed them
LFLAGS =
CFLAGS =

KERN_DIR = /lib/modules/$(shell uname -r)/build/
MOD_SRC = $(shell pwd)
INC_DIR = $(MOD_SRC)/src
SRC_DIR = $(MOD_SRC)/src
BIN_DIR = $(MOD_SRC)/bin

RM = rm -f

SOURCES  = $(wildcard $(SRC_DIR)/*.c)
INCLUDES = $(wildcard $(INC_DIR)/*.h)
OBJECTS  = $(SOURCES:$(SRC_DIR)/%.c=$(BIN_DIR)/%.o)

$(TARGET): $(OBJECTS)
    @$(LINKER) $(OBJECTS) $(LFLAGS) -o $@

$(OBJECTS): $(BIN_DIR)/%.o : $(SRC_DIR)/%.c
    @$(CC) $(CFLAGS) -c $< -o $@

obj-m += $(TARGET).o
    $(TARGET)-objs := $(OBJECTS)

all:
    +make -C $(KERN_DIR) M=$(MOD_SRC) modules
clean:
    +make -C $(KERN_DIR) M=$(MOD_SRC) clean
    $(RM) $(OBJECTS)

My understanding of what it does is:

  • make a list of all .c files and the corresponding location for the .o file

    OBJECTS  = $(SOURCES:$(SRC_DIR)/%.c=$(BIN_DIR)/%.o)
    
  • compile the .c files to create the .o files

    $(OBJECTS): $(BIN_DIR)/%.o : $(SRC_DIR)/%.c
        @$(CC) $(CFLAGS) -c $< -o $@`
    
  • link to the .o files so the program knows what the functions defined in the .h files are

    $(TARGET): $(OBJECTS)
        @$(LINKER) $(OBJECTS) $(LFLAGS) -o $@
    
  • add the .o files as objects of the module $(TARGET)-objs := $(OBJECTS)

The command I'm using to make is

sudo make -j4
Joel
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1 Answers1

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Try, maybe, to tell your compiler where to look for header files:

$(OBJECTS): $(BIN_DIR)/%.o : $(SRC_DIR)/%.c
    @$(CC) $(CFLAGS) -I$(INC_DIR) -I<kernel-folder>/include -c $< -o $@
Renaud Pacalet
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