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Right now %esi contains the base address of an array, let's say 0x601040. When I do x/1db in GDB, I get the value 8, which is the value I want. However, when I try to move the value of %esi from memory into a scratch register, I get another value instead.

What I did was: movl (%esi), %r11d

I printed the si and sil portions to try to get the value 8 as desired, but none of this works as I get different values.

How would I go about getting the byte portion as desired?

Thank you for your assistance.

Rubiks H
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  • why do you use 32bit address on x86-64? Are you sure you are in 64b mode? Hm, probably for sure, because you are using `r11`. Then I would expect the address to be in `rsi`, and use all that, i.e. `movl (%rsi),%r11d` ... that said, either way `r11d` means `r11` register, a it's "dword" part of it, so you are fecthing 4 bytes from address in `esi` (`rsi`), not one byte. Still the bottom byte of `r11` should be equal to 8. If you want 64b zero extended value, you can do `xor r11d,r11d` `movb (%rsi),r11b` (or use `movzx`, but I'm not going even to try to write that in AT&T syntax). – Ped7g Oct 05 '17 at 02:16
  • *I printed the si and sil portions*: That's the pointer. You loaded into `r11`, so you should print `r11b` or `r11w`. – Peter Cordes Oct 05 '17 at 02:21
  • @Ped7g: It's `movz (srcsize)(dstsize)`, so `movzbl (%rsi), %r11d`. The dst-size part can be implied by the dst reg, so `movzb (%rsi), %r11d` works, IIRC. But the src size can't be implied, even with register src (or maybe it can, if you write `movzx`. gas supports both mnemonics in both modes). So AT&T uses separate mnemonics for the different movzx / movsx opcodes (that's how the machine-code works: different opcode for each src size, including what Intel calls `movsxd` for 32-bit src, useful only with 64-bit dst. dst size is controlled in the usual way by `66` operand-size or REX.W.). – Peter Cordes Oct 05 '17 at 02:25

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