Addressing on 32bit and 64bit architectures

Question

If we have a 32bit or 64bit computer architecture, does it mean that we can address 2^32 or 2^64 byte sized memory locations?

Do we always relate addressing with the smallest memory unit byte?

Answer 1

No, and no. (But on "normal" CPUs, sort of and yes.)

x86-64 is a 64-bit architecture with 64-bit integer registers, but it only has 48-bit virtual address space (extensible to 64 in the future if needed). Pointers are 64-bit integers, but the top 16 bits have to be the sign-extension of the low 48 bits. The initial implementations (AMD K8) only supported 40-bit physical addresses. The page-table format allows up to 52-bit physical addresses, but current implementations only support 48-bit (256TiB of RAM).

32-bit x86 has segmentation as well as paging, so it can address 4GiB from each of cs, ss, ds, es, fs, and gs. (This is super inconvenient, so all the major OSes just use a flat 4GiB memory space).

Most 8-bit CPUs could use a pair of 8-bit registers as a 16-bit pointer. AVR (8-bit RISC microcontroller with 32 8-bit registers) still does that.

The terms 32-bit or 64-bit architecture are pretty fuzzy. Does it mean register size, data bus width, pointer width? People (sometimes including the marketing department) call things whatever they want. Skylake-avx512 has a 512-bit path between execution units and L1D cache (for vector loads/stores). So is it a 512-bit SIMD architecture? Yes, I guess so. It's also a 64-bit architecture. AMD Ryzen splits 256b AVX instructions into two 128b halves. Is it a 256-bit SIMD architecture? Sure, why not. Architecturally, the registers are 256b wide. Is it also a 128b SIMD architecture? Yes.

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Most modern architectures are byte-addressable, but some (like maybe DSPs?) are only word-addressable. Each address can be a whole machine word (e.g. 36 bits on some weird CPUs). In that case, 32-bit addresses would get you 4GiB * bytes-per-word of address space, but you'd have to load + shift&mask to use it as that many separate bytes.