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There are a lot of text books and resources that explain addressing mode of the cpu and categorize the X86 addressing mode into 

Immediate 
Register
Memory   -->   direct
         -->   register indirect
         -->   base
         -->   Index
         -->   Base-Index

Basically, addressing mode tries to answer this question: where is the data for the execution of the instruction? For example, mov ax, 04 is immediate because the value 04 is part of the instruction code which is fetched by the cpu. Therefore, no mode memory access is needed for the execution of the instruction.

As another example, mov ax, [FFH] is called direct memory mode because the data (operand) is not available in the instruction code. Hence, cpu has to access the memory one more time to obtain the data.

Now, I see a lot of instances in the disassembly code of an X86 code, compiled with visual studio, that looks like

 mov     dword ptr [ebp-8],0

It is easy to understand that it tries to put 0 in four bytes (dword) of the memory located at [ebp-8]. The instruction code for that is c745f800000000. The question is what is the addressing mode of this instruction (and other instances)?

This is a data movement instruction, so the concept of the addressing mode should be valid. Isn't that?

mahmood
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  • The addressing mode is “indexed” with `ebp` being the index register and `-8` being the displacement. – fuz Oct 20 '17 at 17:46
  • But the value `0` is embedded in the instruction code while it is fetched. So, it should be immediate! – mahmood Oct 20 '17 at 18:28
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    `0`is an immediate. It's encoded in the final four bytes of the instruction. The encoding is `c7` (opcode), `45` (modr/m byte), `f8` (displacement) and `00000000` (32 bit immediate). Note that each operand has its own type, but only one operand can be a memory operand and only that operand has an addressing mode. – fuz Oct 20 '17 at 18:40
  • There was a whole Q&A about each operand having its own addressing mode: [Can an instruction be in two addressing modes at the same time?](https://stackoverflow.com/questions/44861768/can-an-instruction-be-in-two-addressing-modes-at-the-same-time). @mahmood, is your question a duplicate of that? Or are you asking something else. – Peter Cordes Oct 21 '17 at 00:49
  • @fuz: That's not what x86 calls "indexed". There's no index register, just a base + displacement. Related: [Do terms like direct/indirect addressing mode actual exists in the Intel x86 manuals](https://stackoverflow.com/questions/46257018/do-terms-like-direct-indirect-addressing-mode-actual-exists-in-the-intel-x86-man). Naming addressing modes is overrated, especially for x86. It made more sense for m68k because there were some modes that really are special, like post-increment. http://moss.csc.ncsu.edu/~mueller/codeopt/codeopt00/notes/addmode.html – Peter Cordes Oct 21 '17 at 00:57
  • @PeterCordes: It is related but the examples in the answers are not exactly what I wrote. – mahmood Oct 21 '17 at 06:30

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