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AMD states here that the are not affected by Meltdown (i.e. Variant 3), likely not by Variant 2 but by Variant 1 (both SPECTRE). Therefore AMD has released an Microcodeupdate for FAM 17H (i.e. Ryzen) and switched OFF branch prediction. What kind of branch prediction is here turned OFF?

Sadly I only own a mobile SandyBridge* and an AMD Phenomen X4 905e (the updated microcode is only for Ryzen). Can some execute benchmarks like here with a sorted array?
The mentioned update from SUSE just speaks about branch prediction which could mean either Variant 1 (if/else) or Variant 2 (branch jump buffer). Also the people from Google use the term branch prediction for Variant 1 and Variant 2. So it is ambigious what actually was turned OFF.

Why should AMD turn OFF Variant 2 (branch jump buffer), if AMD is likely not affected, due a different implementation. Or is it Variant 1 (if/else), which should slow down probably a lot of work cases dramatically. A pre sorted array is a likely usage case, where branch predicition improves performance.

Thanks

*Add here some finnish profanity...

Peter
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    I seriously doubt branch prediction was turned off because this would have a huge impact on performance. Maybe what they meant is that this microcode adds support for new instructions to clear the BTB upon switching to kernel mode in order to protect from the attacks. – NothingsImpossible Jan 06 '18 at 16:29
  • I also “believe” that AMD didn’t turned it off, more some kind of behaviour change. – Peter Jan 06 '18 at 16:35
  • Related: [why AMD isn't vulnerable to Meltdown](https://stackoverflow.com/questions/48122423/why-are-amd-processors-not-less-vulnerable-to-meltdown-and-spectre/48150015#48150015): Presumably they handle permission-checking for loads differently. That's very plausible. – Peter Cordes Jan 08 '18 at 12:17

1 Answers1

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Seems like AMD has Indirect Branch Restricted Speculation (ibrs) now in usage, restriced but not turned off completely. 

AMD Defaults:
Due to the differences in underlying hardware implementation, AMD X86 systems are not vulnerable to variant #3. The correct default values will be set on AMD hardware based on dynamic checks during the boot sequence.

pti 0 ibrs 0 ibpb 2 -> fix variant #1 #2 if the microcode update is applied
pti 0 ibrs 2 ibpb 1 -> fix variant #1 #2 on older processors that can disable indirect branch prediction without microcode updates

https://access.redhat.com/articles/3311301

So the notice from SUSE isn't really correct.

Peter
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