0

I recently read the GK110 white paper, which claims that each SM has 4 warp schedulers, and each with dual Instruction Dispatch Units. On each cycle, each warp scheduler selects an eligible warp to execute instructions for it.

My question is in GK110, each SM contains 192 CUDA cores (SP), but SM can only schedule 4 warps on each cycle, that is 4 x 32 = 128 cores will be used (assume all threads only need single-precision unit), then what will the other 64 cores do?

talonmies
  • 70,661
  • 34
  • 192
  • 269
StrikeW
  • 501
  • 1
  • 4
  • 11
  • 2
    It is all clearly explained in the Whitepaper if you keep reading. The extra cores are where dual issue comes in. If there are independent instructions from the same warp, they can be issued simultaneously. Think of it as being that there can be up to 6 instructions being executed simultaneously from 4 different warps per SM. – talonmies May 08 '18 at 08:30
  • @talonmies Sorry, I don't fully understand the meaning of *dual issue*. Does it mean that **instruction-level parallelism** for a warp (execute two instructions for a warp simultaneously)? – StrikeW May 08 '18 at 09:55

0 Answers0