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I have to calculate the page table entry with 4k-page physical memory. I have that the segmentation unit generates the address 0x76EE730A and the pin physical address is 0x11BCC30A.

I understand that if the page is 4K then PAE is disabled right? So, i have to separate the physical addres in 10bits/10bits/12bits?

Peter Cordes
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rockstiff
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  • PAE still uses 4k pages, but with 36-bit physical addresses. The fact that the physical address is 32 bits is what tells you that PAE isn't in use. https://en.wikipedia.org/wiki/Physical_Address_Extension. (Unless there's a leading zero that's omitted.) Anyway, no, the *virtual* address is split into 10 / 10 / 12 bits, and those are the offsets in the 2 levels of page tables. – Peter Cordes Jun 10 '18 at 17:19
  • @Peter, PAE supports the full physical address width of the processor. – prl Jun 10 '18 at 17:27
  • @prl: Oh right, wikipedia is only saying that the first CPUs to have PAE were limited to 36 bit physical. But the PTE format is the same as x86-64 ([Why in 64bit the virtual address are 4 bits short (48bit long) compared with the physical address (52 bit long)?](https://stackoverflow.com/q/46509152)), and a legacy-mode kernel on an x86-64 CPU can use the full physical address width of the CPU, up to 52 bits theoretical max. – Peter Cordes Jun 10 '18 at 17:45

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