7

What is this error and what am I supposed to look for?

svalle
  • 81
  • 1
  • 1
  • 6

2 Answers2

28

I got this error when I had done:

wire Q[3:0] when I should have had wire [3:0] Q;

Winston Ewert
  • 44,070
  • 10
  • 68
  • 83
  • Thanks Winston! My error was [Synth 8 - 1717] can not access memory ** directly and this fixed it – Sam Jun 03 '13 at 21:37
1

It's also common under Xilinx Vivado that errors come up if you've imported SystemVerilog code and haven't set the source code type in the system navigator as such. Vivado defaults to making everything basic Verilog, and although pretty much everything in Verilog will synthesize fine if the file type is SystemVerilog, the reverse is not true.

Focus Embedded
  • 11
  • 1
  • This is the correct answer. Even when the port type is consistent you may still see this problem; changing file type solves this problem. – Rock Oct 14 '19 at 21:10