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A write instruction in x86 have release semantics, and this tutorial says the following about what release semantics mean:

Release semantics prevent memory reordering of the write-release with any read or write operation that precedes it in program order.

So if I have the following instructions:

read_instruction_1
read_instruction_2
write_instruction_1
write_instruction_2 (the above instructions will no be reordered to below this instruction)
read_instruction_3
write_instruction_3

The instructions above write_instruction_2 will not be reordered to below write_instruction_2.

But what if I have something like this:

read_instruction_1
read_instruction_2
write_instruction_1
a_non_read_or_write_instruction
write_instruction_2 (will a_non_read_or_write_instruction not be reordered to below this instruction?)
read_instruction_3
write_instruction_3

The a_non_read_or_write_instruction instruction is not a read or write instruction, but I don't want it to be reordered to below write_instruction_2, will it not be reordered to below write_instruction_2?

user8426277
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    Since it's not a read or write, you can't tell the difference. Thus the processor is allowed to reorder it, unless you use a serializing instruction. – Jester Jun 19 '18 at 13:34
  • On Intel CPUs (but not AMD), `lfence` is an *execution* barrier (see [Are loads and stores the only instructions that gets reordered?](https://stackoverflow.com/q/50494658)) so you could use that as a lighter-weight alternative to a full serializing instruction. Are you creating a microbenchmark or something? Otherwise I can't see why you'd need to stop the CPU from running faster. – Peter Cordes Jun 19 '18 at 14:34
  • @Peter Cordes *"I can't see why you'd need to stop the CPU from running faster"* `write_instruction_2` is setting a flag that will be read by another thread, and when the other thread reads this flag, it should assume that all instructions above `write_instruction_2` have been executed. – user8426277 Jun 19 '18 at 16:47
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    @user8426277: If `a_non_read_or_write_instruction` is an input to `write_instruction_2`, then `write_instruction_2` already has to wait for it as an input dependency. If not, then no other thread cares whether some independent register-register local operation in another thread happens before or after the stores execute, or become globally visible (which is a separate thing because of the store buffer). – Peter Cordes Jun 19 '18 at 16:50

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