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The largest possible address size, used to designate a location in memory, is typically a hardware word" What does the above statement really mean? For example in 8086 microprocessor there are 20 bits of address line and 16 bit is the word length, the address of the location is always 20 bits which is more than the word length bits(16 bits), then how maximum possible address size can be a typically hardware word, it more then the word length bits in this case. I might have misunderstood the above statement please clarify me

Michał Turczyn
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pawan097
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  • related: [Data bus width and word size](https://stackoverflow.com/q/47818287/995714), [word size and data bus](https://stackoverflow.com/q/11472484/995714), [Word Sizes and It's Indications](https://stackoverflow.com/q/20523016/995714), [What does it mean by word size in computer?](https://stackoverflow.com/q/19821103/995714) – phuclv Aug 05 '18 at 08:39
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    That's simply not a correct statement IMO (or at least oversimplified). For examples, here's a discussion about an 8-bit CPU with a 16-bit bus: https://electronics.stackexchange.com/questions/57950/how-can-8-bit-processor-support-more-than-256-bytes-of-ram Obviously, in this case the largest possible address is larger than the maximal integer storable in a word. – FK82 Aug 05 '18 at 08:45

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Having one single "word size" is an oversimplification that sometimes fits/works, but especially in the case of x86 it really doesn't1.

Physical addresses (linear addresses) are larger than a word in most 8-bit CPUs, and in 16-bit x86, because it would be inconvenient to have them smaller.

You use multiple registers to create addresses; in 8086 real mode, it's (seg << 4) + offset.

In 8080 or many other 8-bit CPUs, a pair of 8-bit integer registers forms a 16-bit address. (https://retrocomputing.stackexchange.com/questions/5121/why-are-first-four-x86-gprs-named-in-such-unintuitive-order)

Footnote 1: On x86, multiple operand-sizes are natively supported, unaligned memory access (on modern x86) normally has no penalty unless you cross a cache-line boundary, instructions are variable length, etc. Since P5 Pentium 64-bit aligned loads/stores are guaranteed to be atomic (possible only with the FPU, integer registers aren't that wide). So the manual basically guaranteed that the data bus is wider than a register. (Until 16-byte vector registers, and x86-64...)

Many RISC machines are pretty word-oriented (usually 32-bit words), and early physical implementations probably actually had 32-bit busses and so on. Modern 32-bit RISC CPUs often have an FPU that supports 64-bit double, and can usually efficiently load them from cache. They also usually have cache, so transfers to/from memory happen in bursts of 32 or 64 bytes.

So a lot of things are 32-bit in an early 32-bit MIPS microarchitecture.

But even most RISC CPUs like MIPS support byte and halfword loads/stores; most implementations don't have to load/modify/store the containing word to modify a byte. (Unlike a machine with only word-addressable memory).

Peter Cordes
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  • "hardware word" seems to be different from "word". I think the statement the OP is asking about is from the second paragraph of [this](https://en.wikipedia.org/wiki/Word_(computer_architecture)) Wikipedia article. – Hadi Brais Aug 05 '18 at 16:11
  • The Wikipedia article is actually written very well. I think the distinction here is between a word from the perspective of the ISA (e.g., the size of a GPR) and a word from the perspective of the implementation (hardware) (e.g., data bus width). Perhaps the person who has written that statement has done a survey of many processors and noticed that, typically, the address size is the same as the hardware word size. – Hadi Brais Aug 05 '18 at 16:27