I am thinking about Minimizing page faults (and TLB faults) while “walking” a large graph
This is a long shot, but I wish to be able to load data from a page into a register, without updating the “most recent access flag”, as I know that data being loaded from my thread will no be touched again for a long time. Therefore I do not wish to delay the eviction of the page from memory if the OS is getting short of ram.
To my understanding, No.
This is not a thing controlled by the software, the CPU will set the A bit of page structure when it uses it.
To this point, the A bit may even leaks when in a transaction or make a transaction abort (if the CPU need to flip the A bit from 0 to 1).
I believe you are overthinking it, the OS will not rely only on the A bit to implement a LRU policy for the pages.
You can also manually allocate the pages before your critical code starts and deallocate them after it finishes.
If I were you I would focus on considering using prefetchnta + load to avoid polluting the cache too much since it is much smaller than the system memory.
See this nice answer on how to use it and know its pitfalls (it's a brittle pattern).
