Rules of executing shell command in Makefile

Question

When I executed command make, I got an error message

Makefile:4: *** missing separator. Stop.

The command in Makefile is:

$(shell ./makejce common/jce jce)

What's wrong with it?

-------makejce---------

#!/bin/bash
FLAGS=""
local_protoc=""
dir0=`pwd`
dir=`pwd`
......

if [ $# -gt 1 ]
then
    mkdir -p $2
    cd $2
    dir=`pwd`
    cd $dir0
fi

cd $1
jce_dir=`pwd`

#sub dir
for d in `ls -d */`
do
    if [ -d $d ]
    then
            cd $d
            for f in `find . -name '*.jce'`
            do  
                    ${local_protoc} ${FLAGS} --dir=${dir} $f
            done
            cd $jce_dir
    fi
done

#current dir
for f in `ls *.jce`
do
    ${local_protoc} ${FLAGS} --dir=${dir} $f
done

cd $dir0

-----makefile------

......
$(shell ./makejce common/jce jce)
......

This typically occurs when you have target that does not have the ":". But could you give a MWCE ? — kebs, Oct 15 '18 at 12:42
@kebs Do you mean a [mcve]? (Type `[mcve]` to get that in a comment.) — Alfe, Oct 15 '18 at 12:44
@Alfe yep, thanks ! Couln't remember, mixed up" working" and "verifiable"...! — kebs, Oct 15 '18 at 12:55
@WilliamPursell Where? If I add add a tab before line4, the another error occures:`Makefile:4: *** recipe commences before first target. Stop.` — herbertluo, Oct 15 '18 at 13:01
@WilliamPursell I just want to execute a shell command here. — herbertluo, Oct 15 '18 at 13:02
Does this answer your question? [makefile:4: \*\*\* missing separator. Stop](https://stackoverflow.com/questions/16931770/makefile4-missing-separator-stop) — Tejas Shetty, Nov 05 '21 at 08:14

score 2 · Answer 1 · answered Oct 15 '18 at 14:57

With so little info it looks extremely bizarre (why are you running all the build steps in a shell script then invoking that script with a shell makefile function? The entire point of a makefile is to manage the build steps...) but without more information I'll just answer your specific question:

The make shell function works like backticks or $(...) in shell scripts: that is it runs the command in a shell and expands to the stdout of the command.

In your makefile if you have:

$(shell echo hi)

then it runs the shell command echo hi and expands to the stdout (i.e., hi). Then make will attempt to interpret that as some makefile text, because that's where you have put the function invocation (on a line all by itself). That's a syntax error because make doesn't know what to do with the string hi.

If you want to run a shell function then either (a) redirect its output so it doesn't output anything:

$(shell ...command... >/dev/null 2>&1)

or (b) capture the output somewhere that it won't bother make, such as in a variable like this:

_dummy := $(shell ...command...)

(by using := here we ensure the shell function is evaluated when the makefile is parsed).

It works! The `makefile` I post is not the whole file. The other command replaced with `......`. — herbertluo, Oct 16 '18 at 02:08

Rules of executing shell command in Makefile

1 Answers1