I am trying to copy codes between two specific lines from one file and paste it between same two corresponding lines in another file.
For example I have two files test.sv_old and test.sv. I want to copy code from test.sv_old file to test.sv between below two lines
Line 1:"//Start of functional specification here"
Line2:"// Outputs set to 0 if no supply. Uncomment as needed."
Here is the content of test.sv_old file:
`include "def.sv"
/PRIMARY
/SECONDARY
/TERTIARY
/UNASSIGNED
module abc ( );
we want to see this too
//Start of functional specification here
//Functional cell instantiation
abc_real Inst0 (.z1(int_z1),
.z2(int_z2),
.a1(reg_a1));
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // abc
`include "def.sv"
/PRIMARY
/SECONDARY
/TERTIARY
/UNASSIGNED
module xyz ( );
//Start of functional specification here
//Functional cell instantiation
xyz_real Inst0 (.y1(int_y1),
.y2(int_y2),
.a1(reg_a1));
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // xyz
`include "def.sv"
/PRIMARY
/SECONDARY
/TERTIARY
/UNASSIGNED
module lmn ( );
//Start of functional specification here
//Functional cell instantiation
lmn_real Inst0 (.x1(int_x1),
.x2(int_x2),
.a1(reg_a1));
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // lmn
Here is my test.sv file:
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module abc ( );
keep this code untouched
no change needed here
//Start of functional specification here
//Functional cell instantiation
some garbage
here
just replace this
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // abc
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module xyz ( );
keep this as it is
input a1;
//Start of functional specification here
//Functional cell instantiation
some garbage
here and there
why not just replace this
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // xyz
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module lmn ( );
keep this as it is
input a1;
//Start of functional specification here
//Functional cell instantiation
some garbage
here and there
why not just replace this
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // lmn
I have tried below code but it doesn't give me exact output I need:
import sys,re,os
rf_SVFile=open(sys.argv[1],"r")
wtstring = ""
wtindex = 0
copy = False
write = False
print("Copying instantiation code from {} to new SV file {}".format(rf_SVFile.name,sys.argv[2]))
for vline in rf_SVFile:
if vline.strip() == "//Start of functional specification here" and copy == False:
copy = True
elif vline.strip() == "// Outputs set to 0 if no supply. Uncomment as needed.":
copy = False
elif copy:
wtstring = wtstring + vline # wtstring has the functional code between two lines which you want to write to .sv file
with open(sys.argv[2], "r+") as wf_NewSVFile:
insert = False
contents = wf_NewSVFile.readlines()
for index, svline in enumerate(contents):
if svline.strip() == "// Outputs set to 0 if no supply. Uncomment as needed.":
wtindex = index
insert = True
break
contents.insert(wtindex,wtstring) # contents has complete code in list format, instantantiation code is copied from SV file to new SV File
stringContents = "".join(contents) # convert list into string in order to write it to .sv file
if insert:
wf_NewSVFile.seek(0, 0)
wf_NewSVFile.write(str(stringContents))
else:
print(
'Warning: No "/ Outputs set to 0 if no supply. Uncomment as needed." line found in {}, hence code is not being copied to new SV file',NewSVFile)
and here is the modified test.sv file generated by above code:
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module abc ( );
keep this code untouched
no change needed here
//Start of functional specification here
//Functional cell instantiation
some garbage
here
just replace this
//Functional cell instantiation
abc_real Inst0 (.z1(int_z1),
.z2(int_z2),
.a1(reg_a1));
//Functional cell instantiation
xyz_real Inst0 (.y1(int_y1),
.y2(int_y2),
.a1(reg_a1));
//Functional cell instantiation
lmn_real Inst0 (.x1(int_x1),
.x2(int_x2),
.a1(reg_a1));
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // abc
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module xyz ( );
keep this as it is
input a1;
//Start of functional specification here
//Functional cell instantiation
some garbage
here and there
why not just replace this
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // xyz
`include "def.sv"
//PRIMARY
//SECONDARY
//TERTIARY
//UNASSIGNED
module lmn ( );
keep this as it is
input a1;
//Start of functional specification here
//Functional cell instantiation
some garbage
here and there
why not just replace this
// Outputs set to 0 if no supply. Uncomment as needed.
endmodule // lmn
Can anyone explain, what I am doing wrong? Thanks.