I have to write a parser for some makefiles without variables and symbols (\$@, $< etc.), all they contain are Rules as :
Target: Dependencies
[tab] Commands
According to Makefile Grammar , the grammar of Makefile in general is context-sensitive which makes implementing a parser complicated. I tried to write the grammar of the simplified version (Fig below), but I'm not sure if it's correct and if it's context-free.
I didn't detail C (commands) because the shell will parse it.