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If the number of clock cycles it takes to complete an instruction is more than one does that mean program counter gets incremented more than once in the same instruction cycle. I am getting this doubt because from my knowledge registers gets updated on each clock pulse.

Does this mean that if a system is waiting for memory for 3 clock cycles pc will be pc +12?

Karol Dowbecki
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Abishek0398
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  • In a simple non-pipelined microarchitecture that internally does have a single physical register for the program-counter (unlike modern CPUs: [Does Program Counter hold current address or the address of the next instruction?](https://stackoverflow.com/q/52019437)), you'd have an internal "enable" signal for the logic that increments it, which is only true for one clock pulse at the start or end of an instruction, depending on the design. Often start so at least prefetch of the next insn can be pipelined, like in original 8086. – Peter Cordes Nov 08 '18 at 21:43
  • How is the enable signal synchronised with the instruction cycle. Because the clock cycles taken by different instructions are not same.So how will we know that our instruction is completed and we have to increment the pc. – Abishek0398 Nov 09 '18 at 07:07
  • By whatever mechanism figures out which cycle is the last cycle of an instruction. – Peter Cordes Nov 09 '18 at 07:10
  • Ok got it thanks!! – Abishek0398 Nov 09 '18 at 07:12

1 Answers1

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Each instruction cycle of the example processor contains one to x machine cycles. The download phase consists of as many machine cycles as the number of bytes must be sent from the operating memory to the processor under one instruction. The duration of the execution cycle depends on the type of order downloaded.

mansio
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  • I am unable to relate this with program counter Can u please elaborate on that. Thank you! – Abishek0398 Nov 08 '18 at 21:29
  • The PC is a processor register storing information about where the processor sequence is currently located in the instruction sequence. Depending on the processor model, this register stores the address of the currently executed or more frequently the next instruction. It has nothing to do with clock or machine cycle For example in 8080: `CMC` have 4 cycles, but PC is incrementing only by 1, because `cmc` do only 'one' task `CY <- ~ CY`, `MVI A,10` have 7-10 cycles, but PC is incrementing by 2, because have 2 tasks, first decode mvi task ( download phase ) and A<-10 (execution phase). – mansio Nov 08 '18 at 21:45
  • @Abishek0398 here you are for example full list of processor 8080 command ( but in polish) https://pl.scribd.com/document/392709021/AK-Rozkazy8080 Second col is how pc increases and fiveth is how many clock cycles command have. – mansio Nov 08 '18 at 21:54