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I read that the prefetch queue of a CPU can affect the execution of a program and can lead to undesired deviations from expected behaviour (erroneous results).

Is there any method to avoid the above, apart from spacing your commands which affect each other and pray for the best? If not, how much spacing is required spacing?

Are there any other features of x86 family (such as Caches, Pipelines, Superscalar design) which can negatively affect a program? I do not refer to timing (as is the case with pipeline hazards) but to wrong results.

Edit: You all reply that CPU optimizations do not affect correctness, only speed. I am troubled now. For example, in Wikipedia it is claimed that this code will not execute as planned. In addition there are anti debugging tricks, as well as techniques for calculating queue's length, which may well be utilized in order to determine CPU model.

padawan
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  • In case of x86 prefetching has no effect on program correctness only speed. None of the cpu optimizations do, the processor will make sure your code works equivalently to a simple sequential execution. – Jester Dec 10 '18 at 11:54
  • re: your edit: 386 isn't a "modern x86". Unlike P6-family and later, 386 can execute stale instructions, and only re-syncs on a taken branch. – Peter Cordes Dec 11 '18 at 03:07

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No, the CPU obeys the memory-ordering and other rules documented in the manual.

Early prefetch for loads (earlier than the memory model allows) is done speculatively, with a memory-order mis-speculation pipeline flush if the core detects that it used the wrong value for a load.

So modern x86 CPUs are aggressively out-of-order in a lot of ways, but with all the necessary tracking to preserve the illusion of a single thread's instructions running in order. (And for multi-threading, nothing that violates the memory model is actually visible to other threads, just done in cases where it's safe.)

Or the CPU may have stronger / safer behaviour than the manual: e.g. Instruction prefetch actually can't lead to stale instruction execution on modern Intel CPUs: they snoop stores to code addresses that are in flight in the pipeline. Observing stale instruction fetching on x86 with self-modifying code

So the premise of your question is untrue.

Peter Cordes
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