I'm currently developing my own small hypervisor which runs directly on (currently emulated) hardware and utilizes Intel VT-x. I am testing the hypervisor in the x86 Bochs emulator. However, I cannot seems to properly set the Monitor Trap Flag bit so that a VM exit occurs after the current instruction in the guest OS.
Intel SDM does not seems to contain what I am looking for, or at the very least, it is not explained at the place I would expect it to be. My goal is to cause a VM exit after the current instruction, in case said instruction does not cause another VM exit. In my situation, I am using the MTF flag to protect a page in the Extended Page Table (EPT) after I granted access by setting the appropiate bit in the EPT entry for the corresponding GPA. However, the permission is only granted for the length of one instruction; after the instruction succeeded, the VM exit caused by the MTF should protect the page again.
Currently, my implementation causes a MTF VM exit before the instruction is even executed, meaning, right after I set the appropiate bit in the EPTE and subsequently resume the guest OS, the MTF VM exit occurs without the instruction being executed, which causes an infinite loop, since after the MTF VM exit handling the execution resumes to the same instruction, but the page is now protected again, which causes another EPT Violation etc.
I am enabling MTF in the VM-execution controls of the VMCS and my VM-entry Interruption-Information field is set as follows:
static void vmx_store_interruption_information(uint32_t intr_info)
{
vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
}
static void vmx_inject_mtf(struct vcpu_vmx *vmx)
{
/* intr_info = 0x80000700 */
uint32_t intr_info = INTR_TYPE_OTHER_EVENT | INTR_INFO_VALID_MASK;
vmx_store_interruption_information(intr_info);
}
Now, one possibility would be to simply emulate the one instruction, but this would result in a far too complicated approach by creating an opcode table for all possible instructions. Instead, I would like to cause a MTF VM exit after the instruction.