I have a build procedure roughly described by the following Makefile example:
a: b
@echo "Build a, just using b. Don't care about c."
touch a
b: c
@echo "Constructing b from c is cheap..."
touch b
@echo "Once accomplished, I no longer need c."
c:
@echo "Constructing c is very expensive..."
@echo "Work work work..."
touch c
clean:
$(RM) a b c
example: clean
make a
$(RM) c
make a
The point is: I need c
to build b
, but once I have b
, I never again need c
. When I do make example
, make
makes c
, b
, and a
(as expected), deletes c
, and then, in the last make a
invocation, just remakes c
(and does NOT re-make b
and a
, even though, I'd have thought they were stale now). But, since my goal is a
and b
hasn't changed, I don't want to remake c
. Forget about it! Who cares! a
should be considered up-to-date.
Another peculiar thing, is that when I
make a
rm c
make a
(rather than make example
), in the second invocation make
rebuilds everything (while in make example
the second invocation just rebuilds c
).
How do I prevent make
from building c
when its goal is a
and all of a
's immediate prerequisites exist and is fresher than they are (a
isn't stale compared to b
), even though the prerequisites of the prerequisites do not?
Edit: I think that what I may want is to treat every file as old (eg. with --old-file
) unless that file doesn't exist.