Yes, provided that the CPU has 2 free comparers/2 adders, the data are independent of each other and the instruction dispatcher can deliver to both units at the same time. That's how superscalar CPUs work. All x86 CPUs from P5 Pentium as well as all modern CPUs are superscalar.
That's one of the reasons newer microarchitectures run faster than older ones even though clock cycle and the number of cores are still the same, because they can have more execution units, bigger units, bigger cache, run more instructions at the same time along with numerous other improvements. For example
Current x86 processors can deliver 3 instructions per clock cycle. Conroe, however, has been architected to fetch, dispatch, execute and retire up to four full instructions simultaneously, offering a 33% boost over, say, a Pentium 4 CPU
https://hexus.net/tech/tech-explained/cpu/17976-intel-core-2-duo-conroe/
It's hard to define a clear value due to the use of micro-op and macro-fusion. However for some rough comparison, Sandy Bridge is able to achieve 6 micro-ops per cycle. e.g. it can sustain 1 iteration per clock throughput for a loop consisting of two add
instructions with memory sources, a multiply, and a macro-fused dec-and-branch.
See also