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I know that page size is fixed in some operation system, such as pg size is 4K in i386. However, how does memory manager know the size of the page? Does it store it somewhere of memory so that MMU can read it when translating address?

Antu
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Rex.MakeCool
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  • The MMU is part of the i386, and it is probably not the OS telling the MMU what the page size is, but the OS having to work with the page size that the hardware supports: https://stackoverflow.com/questions/11543748/why-is-the-page-size-of-linux-x86-4-kb-how-is-that-calculated – Thilo Jan 27 '19 at 05:44

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Page size has a direct impact in processor architecture. It defines how a page address is interpreted by hardware for the virtual-physical translation.

In-page part of the address (often called offset or displacement) is not translated and is sent unchanged to the cache, while the upper bits (page virtual address) are translated by the TLB, and modifying page size (and offset) would require changes in datapath width. Depending on the size of this offset and on the L1 cache characteristics (size and associativity), the cache can or not use a virtual index which can have a direct performance impact and would imply a redesign. The virtual address size also determines the way page tables are organized and accessed after a TLB miss (page walk). The MMU and cache are a highly critical part of processor design that has a direct performance impact, and they need to be optimized that generally exclude flexibility.

So changing page size requires major changes in the processor architecture and page sizes are generally constant or have a limited number of values. Recent Pentium can have regular 4K or huge 4G pages. Older arm versions (v4 and v5) add subpages that allowed to divide page size by 4. On Arm v8, you can also have 64kB pages. But besides that processor are generally designed for fixed page size, and the operating system must adapt to the processor pages.

Antu
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Alain Merigot
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  • Thanks. So how does processor know its page size? In some 'huge page' mode, page size is bigger. So MMU and TLB must know where the variable 'Page Size' stores? I mainly want to know where it stores in. – Rex.MakeCool Jan 27 '19 at 15:54
  • There is an internal register in the processor that is set during boot time describing it. Boot is done on physical memory and do need a MMU. – Alain Merigot Jan 27 '19 at 17:18
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There a three ways I am aware of that processors define page sizes:

  1. The page size is constant and never changes.

  2. The page size is the same but is configurable. In this case the page size is set in a system register. Usually, the page size had to be certain values so it is a bit setting rather than a numeric value. This seems to be what you are asking. The readers digest version on the intel chips is that setting a bit in the CR4 register switches between 4KB and 4 MB pages.

  3. There are some systems that can have variable page sizes. In that case, the page size is usually set in the page table.

user3344003
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