How to compile with a Makefile in sub-directories?

Question

For a school project I need to create a Makefile that compiles sub-directories without using any other Makefiles. What I mean is that I am not allowed to do this:

make -C <sub-folder>

Here is how it looks like:

In local:

   ./Makefile
   ./sub
   ./sub2

And in sub directory:

   ./sub/file1.c
   ./sub/file2.c
   ./sub/file3.c
   ./sub/file4.c

   ./sub2/file1.c
   ./sub2/file2.c
   ./sub2/file3.c
   ./sub2/file4.c

Here is what I've done so far, but I keep getting errors:

CC              =       gcc -W -Wall -Werror

NAME            =       test

NAME2           =       test2

SRCS            =       sub/file1.c            \
                        sub/file2.c            \
                        sub/file3.c            \
                        sub/file4.c

SRCS2           =      sub2/file1.c            \
                        sub2/file2.c            \
                        sub2/file3.c            \
                        sub2/file4.c

OBJS            =       $(SRCS:.c=.o)

OBJS2           =       $(SRCS2:.c=.o)

all:
    $(OBJS)
    $(CC) $(OBJS) -o $(NAME)

    $(OBJS2)
    $(CC) $(OBJS2) -o $(NAME2)

Thank you, Ephismen.

[EDIT] Edited my problem My problem changed a bit. I need to compile in the same Makefile, always with the same rules, two different binaries. I tried following what worked for one but it doesn't seems to do right for two. If you have any advices please let me know.

The code posted works, but only compiles the first binary.

Just a thought: `SRCS = sub/file1.c sub/file2.c ...` and remove the `cd`s from the target — pmg, Apr 03 '11 at 17:30
Thank you it worked! But I have a second problem now, I am unable to compile two binaries at the same time without using other makefiles. — Aymeric, Apr 03 '11 at 18:07

Robert S. Barnes · Answer 1 · 2011-04-03T18:21:51.597

2

See this article:

Make Tutorial: How-To Write A Makefile

It explains everything including why not to use recursive make and how to do includes instead.

You'll especially want to read: Recursive Make Considered Harmful which explains why recursive make is bad and methods for avoiding it.

edited Apr 03 '11 at 18:21

answered Apr 03 '11 at 18:16

Robert S. Barnes

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Indeed, the [several](http://stackoverflow.com/q/559216/2509) question on Stack Overflow [concerning](http://stackoverflow.com/q/319764/2509) Recursive versus Non-recursive make include links to some well developed make-based build systems. – dmckee --- ex-moderator kitten Apr 03 '11 at 18:41
This tutorial is not good, e.g. it comes to the following conclusion: _So, you will still need to invoke "make clean" ... about 99% of the time_ – anatolyg Apr 03 '11 at 19:02

score 1 · Accepted Answer · answered Apr 03 '11 at 18:13

1

Use the following (remember to put tabs instead of spaces at beginnings of lines):

all: $(NAME) $(NAME2)

$(NAME): $(OBJS)
    $(CC) $(OBJS) -o $(NAME)

$(NAME2): $(OBJS2)
    $(CC) $(OBJS2) -o $(NAME2)

answered Apr 03 '11 at 18:13

anatolyg

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When doing this I get the following error: "Nothing to be done for all". – Aymeric Apr 03 '11 at 18:23
2

@Ephismen This is not an error message; it means `all` (everything) is already made. – anatolyg Apr 03 '11 at 18:50
I was doing two mistakes: first the error message i gave you was wrong, second I had one space hidden very far in Makefile so I was wondering where it was comming from. Anyway thank you very much it works perfectly!! – Aymeric Apr 03 '11 at 18:58

How to compile with a Makefile in sub-directories?

2 Answers2