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I am using the GCC toolchain and the ARM Cortex-M0 uC. I would like to ask if it is possible to define a space in the linker so that the reading and writing operations would call the external device driver functions for reading and writing it's space (eg. SPI memory). Can anyone give some hints how to do it? Regards, Rafal

EDIT: Thank you for your comments and replies. My setup is: The random access SPI memory is connected via SPI controller and I use a "standard" driver to access the memory space and store/read data from it.

What I wanted to do is to avoid calling the driver's functions explicitly, but to hide them behind some fixed RAM address, so that any read of that address would call the spi read memory driver function and write would call the spi write memory function (the offset of the initial address would be the address of the data in the external memory). I doubt that it is at all possible in the uC without the MMU, but I think it is always worth to ask someone else who might have had similar idea.

Rafalf
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  • spi is rarely mapped this way you have to talk through a spi controller. there are possibly rare exceptions but I have not seen one of those in an mcu thus far. – old_timer Apr 18 '19 at 23:04
  • cortex-m has nothing to do with spi it is a core from arm. the chip company adds spi controllers (st, atmel, ti, etc). so this is not a cortex-m question nor an arm question. – old_timer Apr 18 '19 at 23:05
  • if you want to know how to control the linker then that is a fair question if you show what you tried. But if this is a spi question then gcc and linker, etc are also not related tags either. – old_timer Apr 18 '19 at 23:05

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No, this is not how it works. Cortex-M0 has no memory management Unit, and is therefore unable to intercept accesses to specific memory regions.

It's not really clear what you are trying to achieve. If you have connected SPI memory external to the chip, you have to perform all the accesses using a driver, it is not possible to memory map the SPI port abstraction.

If this is an on-device SPI memory controller, it will have two regions in the memory map. One will be the 'memory'region, and will probably behave read-only, one with be the control registers for the memory controller hardware, and it is these registers which the device driver talks to. Specifically, to write to the SPI, you need to perform driver accesses to perform the write.

In the extreme case, (for example Cortex-M1 for Xilinx), there will be an eXecute In Place (XIP) peripheral for the memory map behaviour, and a SPI Master device for the read/write functionality. A GPIO pin is used to multiplex the SPI EEPROM pins between 'memory mode' and çonfiguration mode'.

Sean Houlihane
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