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When I test the cycle number of the module, the results of each test are quite different？

1781344-->First test

1264558-->Second test

1388058-->Third test

I use __rdtsc() to record cycles，and use AVX512 intrinsic。

Are there any methods to make the cycle number of each test basically consistent?

Peter Cordes
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yueluojieying
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1 Answers1

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Completely guaranteed consistent RDTSC counts are impractical. e.g. you'd have to disable interrupts as well as the usual stuff like disable turbo so the CPU runs at constant speed after leaving idle.

(Note that RDTSC on modern CPUs counts reference cycles, not actual core clock cycles. Get CPU cycle count?)

And you'd have to warm up caches + branch prediction + everything and get the CPU to max clock speed before the first timed test. If you're timing tests separately, timing the first one as the "cold" state is actually useful.

In practice people don't disable interrupts, and just ignore high outliers on the assumption that an interrupt or something happened during that test run. You can't disable SMM or NMI anyway.

Peter Cordes
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    SMIs and NMIs cannot be disabled *manually*, but in the SMI handler, all interrupts in including SMIs and NMIs are inhibited automatically. In the NMI handler, NMI interrupts are inhibited automatically, but I don't remember whether SMIs are also inhibited. That said, the chipset may allow the software to manually inhibit NMIs and/or SMIs using the `OUT` instruction, but I cannot think of an example at the moment. – Hadi Brais Apr 25 '19 at 19:18