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I am learning ARM and I am not able to understand the full form of Program Status Register Instructions, MSR and MRS.

Example: 

MRS R0,CPSR         ; Take a copy of the CPSR.
BIC R0,R0,#0x1F     ; Clear the mode bits.
ORR R0,R0,#new_mode ; Select new mode
MSR CPSR,R0         ; Write back the modified CPSR.
tum_
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Sree Ranjani
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    _What_ is in that code that you do not understand? – Matteo Italia May 15 '19 at 06:38
  • Have you had a look at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0311d/ch02s04s02.html ? In your case you are masking (0x1F == 0b11111) the 5 least significant bits (bits 4 to 0) which is the `[4:0] M Mode field` – Stoogy May 15 '19 at 08:26
  • Related: [Setting mode from 'C'](https://stackoverflow.com/questions/22295566/how-can-i-put-arm-processor-in-different-modes-using-c-program). Note that mode setting can be very tricky as it changes the banked registers (most often SP, LR and CPSR). There are better instructions to do this such as `movs pc,lr` which is a typical interrupt return... since you are learning assembler, this is a very difficult place to start. – artless noise May 15 '19 at 16:16

1 Answers1

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The first port of call for ARM instruction set questions is the relevant ARM Architecture Manual. For example, Cortex-M3 uses ARMv7-M.

There you can find:

B5.2.2 MRS Move to Register from Special Register

moves the value from the selected special-purpose register into a general-purpose register.

There are lists of the particular special purpose registers in various places, such as this article, and more definitavely in the architecture manual and the Technical Reference Manual (TRM) for the specific core used in your SoC.

Special Purpose Registers are architecturally defined internal state of the processor, such as the ALU flags, the exception model state, security controls, etc. These are distinct from the r0-r14 'general purpose' registers which are available to the main part of the instruction set. The processor security model will generally restrict access to much of this state (so user code can't escalate it's own priviledge).

Specific instructions are used to access the special purpose registers (and closely linked the co-processor registers) partly so that the relevant permission checks can be provided, and partly to increase the addressable space (at the cost of only providing two types of operation).

Sean Houlihane
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