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My high-level understanding of the Intel front-end is as follows. It is mostly vague and could be wrong.

  • A branch predictor determines the next address to fetch instructions from.

  • Sometimes a signal comes from the backend "branch foo was predicted wrong", causing a pipeline flush and resteer.

  • The instruction fetch unit fetches up to 16 bytes at a time

  • These go through various stages of decoding, until ultimately, the decode units issue μops that flow to the RAT, ROB, and then the backend.

  • However, the μops corresponding to complex instructions like div cannot be directly emitted by any decode unit. When the decode unit detects one of these, it signals the Microcode Sequencer ROM, and μops are issued from there until the instruction is finished being decoded.

My question is: can the MSROM issue branchs? If so, how do they work? Since this is all happening downstream of the branch predictor, which works on (architectural) instructions, how does it know which way to go? Does it just stall after it issues a branch until the backend finishes executing it and it knows whether the condition is true? Does it have some sort of rudimentary static prediction? Or is it actually fed by the the "real" branch predictor somehow, just like the actual architectural instruction stream is?

Brennan Vincent
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    We don't know a whole lot about how microcode branches work inside instructions like `rep movsb`, but we know they can't be *dynamically* predicted like normal branches. Even though my answer on the duplicate isn't as detailed as we might wish, I think it already covers as much as I know re: your questions. – Peter Cordes May 22 '19 at 02:49
  • Thanks, I've been reading through the answer/comments there. Just to sum up and make sure I've understood: is this an accurate summary? "We're pretty sure it does static prediction, but we don't know the exact details of how -- one plausible possibility is that the ops have the static predictions hardcoded in" – Brennan Vincent May 22 '19 at 02:51
  • *When the decode unit detects one of these, it signals the Microcode Sequencer ROM*. My understanding is that it decodes to a sort of "indirect" uop. The MS-ROM isn't accessed by the decoders, only when that "indirect uop" reaches the front of the IDQ and takes over the issue/rename stage. Other than that your explanation looks correct to me. – Peter Cordes May 22 '19 at 02:51
  • Yes, that's an accurate summary of what I currently think is the case. – Peter Cordes May 22 '19 at 02:52

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