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I have a problem with a makefile that I was not able to resolve. I have this structure of files and folders.

├───bin
├───include
│       des.hh
│       des_CR.hh
│       des_CX.hh
│       des_JAK.hh
│       des_JK.hh
│       des_testbench.hh
│       des_VA1.hh
│
├───obj
└───src
        des.cc
        des_CR.cc
        des_CX.cc
        des_JAK.cc
        des_JK.cc
        des_testbench.cc
        des_VA1.cc
        main_des.cc

I write the makefile in this way (here I put a small part):

DESIGN_NAME=des
FULL_NAME=$(basename $(shell find ./src -name $(DESIGN_NAME)'_[A-Z]*.cc' -type f -printf "%f\t"))

EXECUTABLE=bin/$(DESIGN_NAME).x
SYSTEMC=$$SYSTEMC_HOME

LIBDIR = $(SYSC_LIBDIR)
LIBS = $(SYSC_LIBDIR)/libsystemc.a -lpthread

INCDIR = -I./include/ -I. -I$(SYSTEMC)/include/

CXX=g++
CFLAGS= -c

$(EXECUTABLE): obj/main_$(DESIGN_NAME).o obj/$(DESIGN_NAME)_testbench.o obj/$(FULL_NAME).o obj/$(DESIGN_NAME).o
  @echo Building $@
  $(CXX) -g $(INCDIR) -o $@ $^ $(LIBDIR)/libsystemc.a -lpthread

obj/main_$(DESIGN_NAME).o: src/main_$(DESIGN_NAME).cc
  @echo Building $@
  $(CXX) -g $(CFLAGS) $(INCDIR) -o $@ $< 

obj/$(DESIGN_NAME)_testbench.o: src/$(DESIGN_NAME)_testbench.cc include/$(DESIGN_NAME)_testbench.hh
  @echo Building $@
  $(CXX) -g $(CFLAGS) $(INCDIR) -o $@ $< 

obj/$(FULL_NAME).o: src/$(FULL_NAME).cc include/$(FULL_NAME).hh
  @echo Building $@
  $(CXX) -g $(CFLAGS) $(INCDIR) -o $@ $< 

obj/$(DESIGN_NAME).o: src/$(DESIGN_NAME).cc include/$(DESIGN_NAME).hh
  @echo Building $@
  $(CXX) -g $(CFLAGS) $(INCDIR) -o $@ $<

The variable FULL_NAME is used to get a list of all files that starts with "des_" and compile them. All works, except for the fact that when FULL_NAME contains more file names, as it will be, it says this:

g++     src/des_CX.cc   -o src/des_CX
src/des_CX.cc:1:29: fatal error: des_CX.hh: No such file or directory
compilation terminated.
<builtin>: recipe for target 'src/des_CX' failed
make: *** [src/des_CX] Error 1

Every cc file has an include directive like this (obviously with the corresponding correct name):

#include "des_CX.hh"

I repeat, it works if FULL_NAME has only one name, as the other variable, if it has more than one it returns the error.

Any suggestions? Maybe someone knows a better way to get file names, this is an attempt that i made but I'm not sure that it is correct, probably the error is here. Thank you in advance and sorry for the long message.

Silvia
  • 9
  • 4
  • https://stackoverflow.com/questions/48791883/best-practice-for-building-a-make-file/48793058#48793058 – Maxim Egorushkin May 30 '19 at 09:41
  • https://stackoverflow.com/questions/7123431/building-multiple-executables-with-similar-rules/7321954#7321954 – Maxim Egorushkin May 30 '19 at 09:41
  • Possible Duplicate [Makefile to compile all .c files without needing to specify them](https://stackoverflow.com/questions/53136024/makefile-to-compile-all-c-files-without-needing-to-specify-them#53138757) – David C. Rankin May 30 '19 at 10:25
  • 1
    `it works if FULL_NAME has only one name, as the other variable, if it has more than one it returns the error.` You're using multiple targets in a wrong way. [RTFM](https://www.gnu.org/software/make/manual/make.html#Multiple-Targets): "A rule with multiple targets is equivalent to writing many rules, each with one target, and all identical aside from that. The same recipe applies to all the targets, but its effect may vary because you can substitute the actual target name into the recipe using ‘$@’. **The rule contributes the same prerequisites to all the targets also**." – Matt May 30 '19 at 11:57
  • In your case you should use pattern rules instead. – Matt May 30 '19 at 11:59

0 Answers0