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By Memory semantics and model, we understand it by instruction reordering and cache flush/updates around barrier. In the Varhandle class Java, dey have introduced many memory semantics but will little explanation what exactly it does?? I have below question and clarifications required ->

a) Are plain set and get are like normal memory access with no memory ordering restriction and also no visibility gurantee??? b) Opaque memory semantics -> what exactly it does?? Is it a simple memory read and write to main memory(no cache involved) without any memory ordering restriction around it??? Documentation says -> it guarantees ordered access of the same variable for a single thread. c) Difference between aquire/release and volatile??

Thanks

sourabh
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This is what I got from the below docs -> http://gee.cs.oswego.edu/dl/html/j9mm.html Acquire/Release versus Sequentially Consistent memory order

a) plain mode -> Only primitive and reference get and set are atomic, allows all ordering and no cache flush. b) Opaque -> Guarantees visibility of only one variable in program order interthreads. No guarantee/constraint abt other variables visibility inter thread c) Acquire/Release -> Same variable full order guarantee plus happens before guarantee. Does cache invalidate on acquire and cache flush on release d) Volatile -> Completely ordered memory access of all the volatile variables. Completely expected as per program order.

sourabh
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  • the document said that: "Sets the value of a variable to the newValue, in program order,but with no assurance of memory ordering effects with respect to otherthreads. " – HungNM2 Nov 06 '21 at 02:46
  • Opaque will provide coherence (so total order single variable, which is consistent with program order and load sees most recent store before it in that order) + atomicity + progress. – pveentjer Nov 28 '22 at 05:10
  • Acquire/release do not provide full ordering, for that you need sequential consistency. The typical example where acquire/release fails is Dekker's algorithm. So an earlier release-store can be reordered with a later acquire-load to a different address because [StoreLoad] between the 2 accesses is missing. – pveentjer Nov 28 '22 at 05:11
  • There is no cache invalidation and cache flushing involved with any access mode. Cache coherence takes care of keeping the caches in sync. Main memory could be completely out of sync. – pveentjer Nov 28 '22 at 06:04
  • Although release/acquire provide Lamports happens-before semantics, they do not provide JMM happens-before edges. According to the JMM, they are not synchronization operations. Unlike C++. – pveentjer Nov 28 '22 at 06:06