1

I know that in real mode addressing if I want to calculate physical address when I am given the segment+offset I need to use the equation: physical address=segment*16+offset

What I don't got is how there are no colliding in this form. I can simply take address 0x1000:0x0010 that will be translated into pyhsical address 0x10010 and also take pyhsical address 0x1001:0x0000 that will be translated into the same pyhsical address 010010.

Wouldn't it be more efficient to just save 4 bits for segment and 16 bits for offset and then the physical address will be segment<<16 + offset? (and then there is one to one mapping between segment+offset and physical address)

Peter Cordes
  • 328,167
  • 45
  • 605
  • 847
roy cabouly
  • 487
  • 4
  • 12
  • That's right, there are many seg:off pairs that are all the same linear address. Apparently having a small "paragraph" size was useful to avoid wasting memory for things that needed to be segment-aligned. Fortunately real-mode and segmentation are irrelevant most of the time, we can just use 32-bit mode with a flat memory model if we need more than a trivial amount of memory. – Peter Cordes Jul 07 '19 at 10:42
  • 1
    Exact cross-site duplicate on retrocomputing.SE: [Why was segment register value scaled by such a small factor of 16 on i8086?](//retrocomputing.stackexchange.com/q/1016) - yes, paragraph alignment would have wasted more memory if the shift had been larger (8 or 16). The CPU normally works with 8 and 16-bit values, so at least 8-bit segment regs are natural. And since other regs are 16-bit, it makes sense that "special" regs are also 16-bit, even if we didn't have the motivation of using a small shift count. – Peter Cordes Jul 07 '19 at 10:52

0 Answers0