I met a makefile as shown below:
GENERAL_RULES = $(WM_DIR)/rules/General
include $(GENERAL_RULES)/general
#------------------------------------------------------------------------------
# Declare names of make system control files derived from file 'files'
#------------------------------------------------------------------------------
OBJECTS_DIR = $(MAKE_DIR)/$(WM_OPTIONS)
OPTIONS = $(OBJECTS_DIR)/options
FILES = $(OBJECTS_DIR)/files
VARS = $(OBJECTS_DIR)/variables
SFILES = $(OBJECTS_DIR)/sourceFiles
-include $(OPTIONS)
#------------------------------------------------------------------------------
# Declare dependency of all make system files on FILES
# Causes all derived files to be remade if any are changed or missing
#------------------------------------------------------------------------------
all : $(OPTIONS) $(SFILES) $(VARS)
$(OPTIONS) : $(MAKE_DIR)/options
@$(CPP) $(GFLAGS) $(MAKE_DIR)/options | sed -e 's@ *@ @g' > $(OPTIONS)
Can anyone explain the meaning of the last line of code above? There are three @ signs in one single sed command. I didn't quite understand the meaning of the @ sign. Please help.