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I'm currently trying to get some version of the function idle() from the UNIX OS working. I've got the source code, but I'm not good with assembly language (something I've recently been trying to change). Could somebody help me get a better understanding of how it works?

I've tried searching for it, but nothing useful comes up. I've also checked in the book "Lion's Commentary on UNIX", but I didn't find any explanation.

This is the source of the function and that's the link for the full source code.

.globl  _idle
_idle:
    mov PS,-(sp)
    bic $340,PS
    wait
    mov (sp)+,PS
    rts pc
melpomene
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b0kiii
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    Are you looking at the `idle` function, or the `panic` function? – Thomas Jager Jul 30 '19 at 13:37
  • I'm looking for both actually. I'm trying to reimplement some of the UNIX functions such as getfs(), so I stopped on panic(), cause I did not understand idle(). – b0kiii Jul 30 '19 at 13:45
  • @b0kiii : if you find an answer solves your problem you should consider accepting it as an answer (you can also upvote it as well). More on the hows and whys of accepting an answer can be found here: https://meta.stackexchange.com/a/5235/271768 – Michael Petch Jul 30 '19 at 15:10

1 Answers1

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Well this is PDP 11/40 assembly language, which is defined in the manual.

Let's break it down, line by line:

.globl  _idle    # define a global symbol called idle
_idle:           # this is the label for the global symbol
    mov PS,-(sp) # push processor state onto stack
    bic $340,PS  # clear priority level bits - effectively enable all interrupts
    wait         # wait for an interrupt
    mov (sp)+,PS # pop processor state from stack
    rts pc       # return from function

The -(sp) and (sp)+ should be read as the equivalent to the C/C++ operators --sp and sp++.

So, it effectively saves the state, Clears the priority level bits and then waits for an interrupt. Once the interrupt arrives it restores the state and goes back to work.

Please see the section [2.3.2 Processor Status Word] in the manual for the definition of the content of the PS register.

Now, the wait operation will be interrupted for a variety of reasons, not the least of which is the real-time clock interrupt, so it gets woken up periodically to do some more work.

When you look at the source, there are two places where the idle() routine is called - one from the panic handler, in an infinite loop, and the next in the swtch, which swaps between processes and when it doesn't find a runnable process enters the idle routine.

Anya Shenanigans
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    @b0kiii The mask of 340 (octal) is bit pattern 011100000 . Bits 5 through 7 (which are set to 1) are the processor priority level (a value between 0 and 7). So the BIC instruction effectively clears (zeroes) the priority level. A priority level of 0 effectively enables all interrupts and a priority level of 7 locks out interrupts. In essence `idle` simply enables all interrupts and then waits for the next interrupt to occur (similar to doing `STI` `HLT` on x86).When an interrupt occurs an interrupt handler will execute, when it finishes the processor continues at the instruction after `wait` – Michael Petch Jul 30 '19 at 14:42
  • May I ask, why are the '+' and '-' around sp? – b0kiii Jul 30 '19 at 14:43
  • @MichaelPetch Thank you for the detailed explanation. It was extremely useful! – b0kiii Jul 30 '19 at 14:45
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    @b0kiii The + before and after the parentheses act like the `++` operator in C (and `-` is similar to `--`). `mov PS,-(sp)` decrements `sp` by one word FIRST and then PS (processor status) is stored at the memory address pointed to by `sp`. That is similar to a `PUSH` instruction on x86. `mov (sp)+,PS` moves what is at the memory address pointed to by SP and moves it to PS, and then AFTER it increments SP by one word. That is like the `POP` instruction on x86 – Michael Petch Jul 30 '19 at 14:47
  • @b0kiii : It is really no coincidence that pre and post increment `++` and pre and post increment `--` in the _C_ language map to the pre increment and post increment on PDP memory operands. _C_ was originally designed to leverage the PDP processors and their instructions. – Michael Petch Jul 30 '19 at 14:55
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    @MichaelPetch Oh, now it makes perfect sense. I appreciate your help. Have a nice day. – b0kiii Jul 30 '19 at 14:59