0

I have this:

$ cat Makefile
run:
    echo "${var}"

When I invoke it like this, I get incorrect result for the second case below:

First case

$ make run var='hah(617'
echo "hah(617"
hah(617 #correct

Second case

$ make run var='hah$^hj'
echo "hahhj" 
hahhj # incorrect, should be hah$^hj

How do I fix the Makefile ?

tripleee
  • 175,061
  • 34
  • 275
  • 318
Ankur Agarwal
  • 23,692
  • 41
  • 137
  • 208
  • As a workaround you can replace $ with \$$; make run var='hah\$$^hj' Unfortunately that doesn't explain why make behaves so unintuitively, nor does it help solving it in the makefile itself – user1372408 Aug 20 '19 at 03:56
  • Yeah I'd like to solve this in Makefile – Ankur Agarwal Aug 20 '19 at 03:57
  • `why make behaves so unintuitively` Consider that make has both "simple" and "recursive" variables, unlike shell which only knows "simple" ones. Therefore, you can't easily [export all make variables into the environment](https://stackoverflow.com/questions/56467690/how-to-improve-call-eval-call-paradigm-in-using-make). Therefore, while writing a recipe, you **must** have some way to differ between make's variables (`CC`, `CFLAGS` etc.) and shell/environment variables. – Matt Aug 20 '19 at 04:52

0 Answers0