While reading this question I encountered the terms “false sharing” and “true sharing”. I read what false sharing is, but I can’t find anything on true sharing. Although in the mentioned question the term is described as “constructive interference” I still don’t understand what it means.
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5It would be nice if you repeat the essential parts as a cite in your quesiton, instead of just the link. It's a bit tedious to go forth and back from the linked question. – πάντα ῥεῖ Aug 22 '19 at 10:25
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This is what I have understood of true sharing and false sharing from a hardware design perspective. Correct me if I am wrong.
Cores load a block of memory when they access variables, to reduce memory access time. In a multi core system, coherency between these "cache lines" is to be maintained. Even then, cache miss can occur due to variety of reasons, two of them being a result of two types of sharing of data.
A "true sharing of data" where two cores, try to access and modify the same word, resulting in continuous invalidation of the cache line in the other core. Lets say cache line size is 2 words, core 0 and core 1 are trying to modify address 0x100. Assuming byte storage, 2 word cache line size would mean 0x100 ~ 0x108 would be loaded into caches of core 0 and core 1. Now when core 0 modifies data at 0x100, cache line incore 1 is invalidated. When core 1 modifies the data at 0x100 it has to update its cache line with data from core 0 cache, and cache line in core 0 is invalidated. After this it will write to 0x100. Now if this is happening in a loop, lot of bandwidth is wasted in cache maintenance. This is cache miss due to True Sharing where there is a "true sharing" of data word between cores.
Second type is a "false sharing of data" where two cores, try to access and modify the two different words within the same cache line, resulting in continuous invalidation of the cache line in the other core. Taking the previous example, let's assume core 0 wants to modify 0x100 and core 2 wants to modify 0x104. Now when core 0 modifies data at 0x100, core 1 cache line is invalidated. When core 1 modifies the data at 0x104 it has to update its cache line with data from core 0 cache and cache line in core 0 is invalidated. After this it will write to 0x104. This too will cause loss of performance when done in a loop. Here the performance loss is due to "false sharing" of data between two cores.
TheYellowFlash
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As I understand it, true sharing refers to the problem of multiple cores frequently writing to the same shared variable, while false sharing refers to multiple cores writing to different variables that are on the same cache line.
In both cases caches have to be frequently invalidated in order to load the most recent version, but true sharing cannot be fixed by e.g. adding padding to make sure two variables are on different cache lines.
References:
Entimon
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True sharing is one core accessing multiple nearby memory addresses that have been loaded into a single cache line. Every access after the first benefits from the cache.
Caleth
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And two different cores do not access the data belonging to the other core, no? – TonySalimi Aug 22 '19 at 10:45
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OK, thanks. So the problem is that on one hand the cache line should be as large as possible, that there will be many true sharings and little cache misses, and on the other hand it should be as small as possible, so there will be little false sharings and cache line invalidations will require less memory to be re-fetched. Am I right? – Aug 22 '19 at 10:59
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@YanB. There are other (physical / electrical) considerations for cache line sizes. Also, if you are visiting *every* word in a range, the size of the cache line doesn't matter. – Caleth Aug 22 '19 at 13:00
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@Jean-BaptisteYunès Yes. data with spacial locality sees a performance benefit from any true sharing that occurs accessing it – Caleth Aug 22 '19 at 13:01
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This shouldn't be the accepted answer. The concept of "True sharing" is more what @TheYellowFlash described. See reference here for example: https://inst.eecs.berkeley.edu/~cs61c/resources/su18_lec/Lecture20.pdf#page=56 – Entimon Feb 15 '22 at 13:08
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@Entimon the answer in the linked question is using it in this sense. In most cases, you don't care whether it's the same bits that both cores are operating on, or just nearby bits, for the slowdown associated by maintaining a coherent set of caches. And your link doesn't call it true sharing, but real sharing. – Caleth Feb 15 '22 at 13:48
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@Caleth The link does call it true sharing (in the bottom). I am confused by the way this term is used in your answer and in the code comment of the referenced SO question, because it suggest a performance benefit, but I think that term is generally used to describe a performance decrease. See also e.g. here: http://thebeardsage.com/true-sharing-false-sharing-and-ping-ponging/ – Entimon Feb 16 '22 at 14:30
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@Entimon I explained the use that OP is asking about. There seems to be an overloading of this term. – Caleth Feb 16 '22 at 14:39
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@Caleth I see. If that's the case, could you maybe add an example reference to your answer where the concept you're referring to is described in more detail? For future visitors to be able to put it into the right context it would be helpful, I think... – Entimon Feb 16 '22 at 15:09
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Visit link below for detailed article on true and false sharing: https://articlesforengineers.blogspot.com/2023/07/true-sharing-and-false-sharing.html
EngR. HaSSan
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Link-only answers tend to be downvoted here and one reason is that the link could go stale in the future and make the answer useless. In addition to providing a link it is suggested that you also include a summary of the link here. – Weijun Zhou Jul 12 '23 at 11:59