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I'm having some trouble with my first bigger makefile project. I got a bigger Library i'm using in my c++ project. More accurate: In my .cpp files and .h files I need to include some headers out of this bigger library.

Here's my structure, to let you know how I'm using the library in my project:

myproj
  |
  |____Makefile
  |____main.cpp
  |____init.cpp
  |____end.cpp
  |____init.h
  |____end.h
  |____Dependencies
           |____biggerlib
                   |____bin   
                           |____...
                   |____include
                           |____#more directories including
                                #the Library headers
                           |____...
                   |____src
                           |____biggerLib1
                           |____biggerLib2
                                   |____biggerLibrary.cpp
                                          |____...
                                   |____Lib2.cpp
                                          |____...
                                   |____Lib3.cpp
                                          |____...
                                   |____Util
                                          |____DebugOut.cpp
                                   |____Dev
                                   |____Data
                                          |____etc.
                   |____makestuff
                           |____...
                           |____...
                                   |____...
                           |____...
                   |____codestuff
                           |____...
                           |____...
                                   |____...
                           |____...
                   |____etc.

I'm not allowed to change that structure.

So, my problem is, that if I start make, gcc or g++ does not find my input files. Error code:

g++: fatal error: no input files
compilation terminated.
*makefileName*:21: recipe for target '*Name*' failed
make: *** [*Name*] Error 1

Therefore, here some out of my makefile: At first my OBJECTS file:

OBJECTS += \
$(BUILD)main.o \
$(BUILD)init.o \
$(BUILD)end.o 

Then my makefile:

#Name (output name / project name)
NAME = proj

#Compiler directory
CC = gcc
CPP = g++
#Libray directorys
SDCC = /home/myname/myproj/Dependencies/biggerlib/src/biggerLib2/Util

# the headers are working well since yesterday but now i got the trouble with the input stuff...

#C-Flags for object-compiling
CFLAGS = -O2 -g3 -c -I$(SDCHDR) -I$(SDCDATAMODEL) -I$(SDCPOCO) #may i have to add here the source files too? did not work...

#Main-target (linking)
$(NAME) : $(OBJECTS)
    $(CPP) -o $(NAME) -I$(SDCC)/DebugOut.cpp ## this one was just to try if I could bind in one single .h file... 

#Object-targets
%.o : %.cpp 
    $(CPP) -o $@ $< $(CFLAGS)

My make command:

make -f makefilename

So it would be nice, if anyone of you know how I could include my missing input files, without changing the directory structure.

  • Possible duplicate of [How to generate a Makefile with source in sub-directories using just one makefile](https://stackoverflow.com/questions/231229/how-to-generate-a-makefile-with-source-in-sub-directories-using-just-one-makefil) – j2ko Sep 06 '19 at 09:38
  • I think cmake is easy to scale out with, you could try look into cmake for your new project; it's a build generator tool. – Tagger5926 Sep 06 '19 at 09:54
  • Cmake is probably not an option for me :( I need to do it with make to include it laer in an other makefile in a waay bigge project – Kai Schoening Sep 06 '19 at 09:58
  • Guessing won't work! You never set `$(OBJECTS)` and you tried to pass your source file as an include path. What reference material are you using when constructing your makefile? – Lightness Races in Orbit Sep 06 '19 at 10:10
  • I did set them, but didnt show you because i thought this wont be necessary for yall. i have an extern object file – Kai Schoening Sep 06 '19 at 10:14
  • Please include the values of `$(NAME)` and `$(OBJECTS)` (at least in abbreviated form) - it's very important when debugging makefiles. Also please include the first target, if it's different than `$(NAME)`, and the exact `make` command you're running. – root Sep 09 '19 at 05:37
  • okei i added the $(NAME) and $(OBJECTS) and my make command – Kai Schoening Sep 09 '19 at 06:16

0 Answers0